This thesis proposes and demonstrates Time to Digital Converters (TDC) with high resolution realized in 65-nm digital CMOS. It is used as a phase detector in all digital PLL working with 5GHz DCO and 20MHz reference input for radio transmitters. Two kinds of high resolution TDC are designed on schematic level including Vernier TDC and parallel TDC. The Sensed Amplifier Flip Flop (SAFF) is implemented with less than 1ps sampling window to avoid metastability. The current starved delay elements are adopted in the TDC and the conversion resolution is equal to the difference of the delay time from these delay elements. Furthermore, the parallel TDC is realized on layout and finally achieves the resolution of 3ps meanwhile it consumes average power 442μW with 1.2V power supply. Measured integral nonlinearity and differential nonlinearity are 0.5LSB and 0.33LSB respectively.

No description available.

Vision has always been one of the most important cognitive tools of human beings. In this regard, the development of image sensors opens up the potential to view objects that our eyes cannot see. One of the most promising capability in some image sensors is their single-photon sensitivity that provides information at the ultimate fundamental limit of light. Time-resolved single-photon avalanche diode (SPAD) image sensors bring a new dimension as they measure the arrival time of incident photons with a precision in the order of hundred picoseconds. In addition to this characteristic, they can be fabricated in complementary metal-oxide-semiconductor (CMOS) technology enabling the integration of complex signal processing blocks at the pixel level. These unique features made CMOS SPAD sensors a prime candidate for a broad spectrum of applications. This thesis is dedicated to the optimization and characterization of quantum imagers based on the SPADs as part of the E.U. funded SUPERTWIN project to surpass the fundamental diffraction limit known as the Rayleigh limit by exploiting the spatio-temporal correlation of entangled photons. The first characterized sensor is a 32×32-pixel SPAD array, named “SuperEllen”, with in-pixel time-to-digital converters (TDC) that measure the spatial cross-correlation functions of a flux of entangled photons. Each pixel features 19.48% fill-factor (FF) in 44.64-μm pitch fabricated in a 150-nm CMOS standard technology. The sensor is fully characterized in several electro-optical experiments, in order to be used in quantum imaging measurements. Moreover, the chip is calibrated in terms of coincidence detection achieving the minimal coincidence window determined by the SPAD jitter. The second developed sensor in the context of SUPERTWIN project is a 224×272-pixel SPAD-based array called “SuperAlice”, a multi-functional image sensor fabricated in a 110-nm CMOS image sensor technology. SuperAlice can operate in multiple modes (time-resolving or photon counting or binary imaging mode). Thanks to the digital intrinsic nature of SPAD imagers, they have an inherent capability to achieve a high frame rate. However, running at high frame rate means high I/O power consumption and thus inefficient handling of the generated data, as SPAD arrays are employed for low light applications in which data are very sparse over time and space. Here, we present three zero-suppression mechanisms to increase the frame rate without adversely affecting power consumption. A row-skipping mechanism that is implemented in both SuperEllen and SuperAlice detects the absence of SPAD activity in a row to increase the duty cycle. A current-based mechanism implemented in SuperEllen ignores reading out a full frame when the number of triggered pixels is less than a user-defined value. A different zero-suppression technique is developed in the SuperAlice chip that is based on jumping through the non-zero pixels within one row. The acquisition of TDC-based SPAD imagers can be speeded up further by storing and processing events inside the chip without the need to read out all data. An on-chip histogramming architecture based on analog counters is developed in a 150-nm CMOS standard technology. The test structure is a 16-bin histogram with 9 bit depth for each bin. SPAD technology demonstrates its capability in other applications such as automotive that demands high dynamic range (HDR) imaging. We proposed two methods based on processing photon arrival times to create HDR images. The proposed methods are validated experimentally with SuperEllen obtaining >130 dB dynamic range within 30 ms of integration time and can be further extended by using a timestamping mechanism with a higher resolution.

This thesis investigates the use of field-programmable gate arrays (FPGAs) to implement a time-to-digital converter (TDC) with on-chip calibration and temperature correction.Using carry-chains on the Xilinx Kintex UltraScale architecture to create a tapped delay line (TDL) has previously been proven to give good time resolution.This project improves the resolution further by using a bit-counter to handle bubbles in the TDL without removing any taps.The bit counter also adds the possibility of using a wave-union approach previously dismissed as unusable on this architecture.The final implementation achieves an RMS resolution of 1.8 ps.

Three main analog circuit building blocks that are important for a mixed-signal system are investigated in this work. New building blocks with emphasis on power efficiency and compatibility with deep-submicron technology are proposed and experimental results from prototype integrated circuits are presented. Firstly, a 1.1GHz, 5th order, active-LC, Butterworth wideband equalizer that controls inter-symbol interference and provides anti-alias filtering for the subsequent analog to digital converter is presented. The equalizer design is based on a new series LC resonator biquad whose power efficiency is analytically shown to be better than a conventional Gm-C biquad. A prototype equalizer is fabricated in a standard 0.18μm CMOS technology. It is experimentally verified to achieve an equalization gain programmable over a 0-23dB range, 47dB SNR and -48dB IM3 while consuming 72mW of power. This corresponds to more than 7 times improvement in power efficiency over conventional Gm-C equalizers. Secondly, a load capacitance aware compensation for 3-stage amplifiers is presented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load while consuming as low as 1.2mW of quiescent power. It can deliver a maximum RMS power of 20mW to the load with -84.8dB THD and 92dB peak SNR, and it occupies a small area of 0.1mm2. The power consumption is reduced by about 10 times compared to drivers that can support such a wide range of capacitive loads. Thirdly, a novel approach to design of ADC in deep-submicron technology is described. The presented technique enables the usage of time-to-digital converter (TDC) in a delta-sigma modulator in a manner that takes advantage of its high timing precision while noise-shaping the error due to its limited time resolution. A prototype ADC designed based on this deep-submicron technology friendly architecture was fabricated in a 65nm digital CMOS technology. The ADC is experimentally shown to achieve 68dB dynamic range in 20MHz signal bandwidth while consuming 10.5mW of power. It is projected to reduce power and improve speed with technology scaling.

Cette thèse aborde le problème de génération d'horloge globale dans les SoCs complexes dans le contexte des technologies CMOS profondément submicroniques. Actuellement, afin de contourner les difficultés liées aux techniques classiques de distribution d'horloge (p.ex. arbre, grille) dans les systèmes synchrones, les concepteurs qui désirent de se rendre sur le paradigme Synchronisation Globale se tournent vers les techniques de synchronisation rompant avec les approches classiques (par exemple oscillateurs distribués, les ondes stationnaires , oscillateurs couplés, les retards programmables). Cette étude s'inscrit dans ce courant. Dans ce travail, nous avons étudié et mis au point un système de génération d'horloge sur puce destiné à un SoC synchrone de haute fiabilité. Cette architecture est basée sur un réseau d'oscillateurs couplés en phase et en fréquence à l'aide d'un réseaux de boucles à verrouillage de phase tout numériques (ADPLLs). Pendant cette recherche nous avons mis au point les spécifications et choisi une architecture de réseau. Un modèle théorique du système a été mis en place en collaboration avec CEA-LETI et Supélec dans le cadre du projet ANR HODISS. Nous avons analysé le comportement du système dans les simulations sur différents niveaux d'abstraction, en enquêtant des conditions de stabilité de son fonctionnement synchrone. L'ADPLL a été proposé comme un nœud élémentaire du réseau de synchronisation distribuée. L'utilisation d'ADPLL permet de contourner les difficultés d'implémentation, qui sont généralement associées à PLL analogique. Nous avons conçu les blocs principaux de l'ADPLL: un oscillateur à commande numérique (Digitally-Controlled Oscillator, DCO), un détecteur de phase/fréquence (PFD) et un bloc de traitement d'erreur. Une technique de conception basée sur les cellules a été adapté pour le développement d'oscillateur. Cette technique réduit considérablement la complexité de l'implémentation de l'oscillateur. Les autres blocs ont été conçus en utilisant un flot de conception numérique commun. Afin de réduire les risques associés à l'implémentation de silicium, le système a été validé dans une plate-forme de prototypage FPGA. Les résultats des mesures ont montré que la synchronisation de réseau se comporte comme prédit par la théorie et ainsi que les simulations. Deux circuits de prototypage ont été conçus, mis en œuvre et testés dans une technologie CMOS 65 nm de STMicroelectronics. La première puce est une preuve de concept d'un DCO conçu très linéaire et monotone. Les paramètres mesurés de l'oscillateur sont conformes aux spécifications. La performance mesurée a démontré une gigue de moins de 15 ps rms, en consommant 6.2 mW/GHz @ 1.1 V. La plage de réglage de l'oscillateur est 999-2480 MHz avec une résolution de 10 bits. La deuxième puce est un réseau d'horloge avec 4x4 nœuds qui se compose de 16 ADPLLs distribués. Chacun d'entre eux utilise les blocs conçu précédemment: DCO, PFD et bloc de traitement d'erreur. Les expérimentes ont montré que la technique proposée de génération d'horloge distribuée est réalisable sur une puce réelle CMOS. La performance mesurée démontre l'erreur de synchronisation entre les oscillateurs voisins moins de 60 ps, alors que la consommation d'énergie est 98.47 mW/GHz.

No description available.

A scheme for Built-in-Self-Test (BIST) of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner is presented in this thesis. With technology scaling, the inverter switching times are becoming shorter thus leading to better resolution of edges in time. This time resolution is observed to be superior to voltage resolution in the face of reducing supply voltage and increasing variations as physical dimensions shrink. In this thesis, a new method of observability of analog signals is proposed, which is digital-friendly and scalable to future deep sub-micron (DSM) processes. The low-bandwidth analog test voltage is captured as the delay between a pair of clock signals. The delay thus setup is measured digitally in accordance with the desired resolution. Such an approach lends itself easily to distributed manner, where the routing of analog signals over long paths is minimized. A small piece of circuitry, called sampling head (SpH) placed near each test voltage, acts as a transducer converting the test voltage to a delay between a pair of low-frequency clocks. A probe clock and a sampling clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head, present at each test node consists of a pair of delay cells and a pair of flip-flops, giving rise to as many sub-sampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding sub-sampled signal pair is fed to a Delay Measurement Unit (DMU) to measure the skew between this pair. The concept is validated by designing a test chip in UMC 130 nm CMOS process. Sub-mV accuracy for static signals is demonstrated for a measurement time of few milliseconds and ENOB of 5.29 is demonstrated for low bandwidth signals in the absence of sample-and-hold circuitry. The sampling clock is derived from the probe clock using a PLL and the design equations are worked out for optimal performance. To validate the concept, the duty-cycle of the probe clock, whose ON-time is modulated by a sine wave, is measured by the same DMU. Measurement results from FPGA implementation confirm 9 bits of resolution.

With the move of the broadband cellular network towards 5G taking off and the preparatory work on 6G and beyond starting, the need for low-complexity, low-power, and high-performance frequency synthesis using Phase-Locked Loop (PLL)s increases. As we get deeper into the mm-wave frequencies and push towards frequencies in the order of 50-70 GHz design challenges with existing PLL architectures, such as limited technology scaling and limited in-band noise performance become more apparent. Other designs have tried overcoming these problems, for example by using single-bit phase detection at the cost of increased complexity when trying to control the bandwidth, or designing the loop with lower bandwidth to suppress in-band noise at the cost of requiring a lower noise and thus more power hungry oscillator. This thesis proposes a new Phase-locked loop architecture implemented in a 22nm node to combat these issues, utilizing a Pulse-Shrinking Time-To-Digital Converter (PS-TDC) offering sub-pico-second resolution with minimal power consumption in lock. The results found in this thesis have shown the viability of such a design, offering good in-band performance, allowing for wide bandwidth, and the use of a cheaper low-power Digital-Controlled Oscillator (DCO). The PS-TDC architecture combined with control logic implemented in this project can drastically decrease power consumption in lock while being able to compensate for process variations to optimize jitter performance. Additionally, by utilizing a Phase-Frequency Detector (PFD) and gear-shifting logic it has been shown that robust and fast locking can be achieved. / Med övergången till 5G i mobila bredbandsnätverk och förberedelserna för 6G på gång ökar behovet av lågkomplexa, lågeffekts- och högpresterande frekvenssyntes. När vi beger oss djupare in i millimetervågsfrekvenserna och strävar efter frekvenser uppemot 50-70 GHz blir designutmaningar med befintliga faslåsta loopar, såsom begränsad teknologiskalning och dålig prestanda för inband-brus, alltmer tydliga. Andra designer har försökt att övervinna dessa problem genom att till exempel använda enbitars fasdetektion till priset av ökad komplexitet vid styrning av systemets bandbredd, eller genom att designa loopen med lägre bandbredd för att vidare dämpa inband-brus, vilket kommer till priset av en oscillator med lägre brus och därmed högre effektförbrukning. Denna avhandling föreslår en ny arkitektur för faslåsta loopar för att överkomma dessa problem genom att använda en pulskrympande tids-till-digital omvandlare som erbjuder sub-pikosekunds upplösning med minimal effektförbrukning när frekvensen är låst. Resultaten som presenteras i denna avhandling har visat att en sådan design är möjlig, med god in-band prestanda, möjlighet till hög bandbredd och därmed användning av en billigare lågeffekt DCO. Den pulsskalande TDC-arkitekturen i kombination med kontrolllogik implementerad i detta projekt kan dramatiskt minska effektförbrukningen när frekvensen är låst, samtidigt som den kan kompensera för processvariationer för att optimera jitterprestanda. Sist har det visats att en robust och snabb låsning av frekvensen kan uppnås genom att använda en PFD.

Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014