abstract: Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2019

De nombreux dispositifs embarqués récents comme les téléphones portables, les GPS ou encore les consoles de jeu, possèdent un ou des haut-parleurs, chacun étant piloté par un amplificateur audio sur circuit intégré. De tels amplificateurs audio doivent répondre le mieux possible à quatre contraintes : une qualité audio satisfaisante, une immunité aux perturbations induites par le système, une faible consommation et une surface de silicium minimale. Ce travail de thèse sous contrat CIFRE a pour origine la création de l’entreprise Primachip en mai 2009 par Christian Dufaza et Hassan Ihs. Cette startup a été bâtie sur une architecture innovante d’amplificateur audio de classe D intégré. Son originalité repose sur le principe de rétroaction partielle qui s’applique à une boucle contenant un modulateur numérique Delta Sigma (ΔΣ) qui pilote l’étage de puissance et un convertisseur analogique-numérique (ADC) effectuant la rétroaction. Cela permet d’obtenir la stabilité de cette boucle tout en offrant une excellente réjection des bruits de l’étage de puissance. Un prototype sur silicium de l’architecture d’amplificateur de classe D numérique a été conçu et fabriqué. Un nouvel ADC ΔΣ temps continu a été développé pour ce prototype, afin d’obtenir des performances supérieures ou égales à l’état de l’art. Les résultats obtenus sur le circuit se sont révélés encourageants, bien que toutes les spécifications n’aient pas été atteintes. L’analyse des erreurs de ce premier circuit doit permettre la réalisation d’un amplificateur intégré exploitant au mieux cette architecture de classe D numérique. / Most current embedded devices, such as smartphones, GPS or portable consoles, feature one speaker or more, those speakers being driven by an integrated audio amplifier. This type of amplifier must meet four specifications: an adequate audio quality, to be immune to system disturbances, low power consumption and the smallest silicon area. This work takes its origin from the creation of Primachip in May 2009 by Christian Dufaza and Hassan Ihs. The aim of this startup was to develop and sell an innovative audio class-D amplifier for mobile market: the digital class-D concept. A partnership with the IM2NP laboratory was decided to propose a PhD topic under CIFRE contract (PhD in an industrial environment), in order to study and improve the amplifier architecture. Its originality is in the partial feedback concept which applies to a loop made of a digital ΔΣ modulator driving the power stage, with an analogue-to-digital converter (ADC) in the feedback path. It makes it possible to achieve stability while offering an outstanding power supply rejection. An integrated prototype of the class-D amplifier was designed, fabricated and evaluated. A new continuous-time ΔΣ ADC has been added to enable the digital class-D loop to achieve performances superior or equal to state of the art. The circuit measurement results were encouraging, although not ideal. The analysis of the prototype errors was performed. The conclusions should allow the design of an integrated audio amplifier making the best of the digital class-D architecture.

The presented dissertation thesis deals with a novel structure of delta-sigma () modulator which compensates influence of higher harmonic distortion and therefore it is possible to achieve high resolution up to 16 bits. This novel proposed structure combines advantages of one bit quantizer modulators with mutli-bit modulators. The novel second order structure is presented, correct function is verified in MATLAB simulation enviroment and requirements for partial block are studied. The second part of the work deals with design of converter with novel structure of modulator using switched capacitor technique utilizing ONSemi I3T25 technology. Advantages and disadvantages of the novel structure are evaluated and novel structure is compared with common structures of modulators.

The rapid development in the semiconductors industry has enabled the placement of multiple chips on a single die. This has helped boost the functionality of modernday application specific integrated circuits (ASICs). Thus, digital circuits are being increasingly placed along-side analog and RF circuits in what are known as mixed signal circuits. As a result, the noise couplings through the substrate now have an increased role in mixed-signal ASIC design. Therefore, there is a need to study the effects of substrate noise and include them in the traditional design methodology. ∆Σ analog-to-digital converters (ADCs) are a perfect example of digital integration in traditionally analog circuits. ADCs, used to interface digital circuits to an analog world, are indispensable in mixed-signal systems and therefore set an interesting case study. A ∆Σ ADC is used in this thesis to study the effects of substrate noise. A background study is presented in the thesis to better understand ∆Σ modulators and substrate couplings. An intensive theoretical background on generation, propagation and reception of substrate noise is presented in light of existing researches. System and behavioural level models are proposed to include the effects of substrate noise in the design stages. A maximum decay of 10dB is seen due to injection of substrate noise system level simulations while a decay of 12dB is seen in behavioural simulations. A solution is proposed using controlled clock tree delays to overcome the effects of substrate noise. The solution is verified on both the system and behavioural levels. The noise models used to drive the studies can further be used in mixed-signal systems to design custom solutions. / Den snabba utvecklingen inom halvledarindustrin har möjliggjort placering av flera marker på en enda dö. Detta har hjälpt till att öka funktionaliteten hos moderna applikationsspecifika integrerade kretsar. Sålunda placeras digitala kretsar i allt högre grad parallella och RF-kretsar i de så kallade blandade signalkretsarna. Som ett resultat har bullerkopplingarna genom substratet nu en ökad roll i ASICdesign med blandad signal. Därför finns det behov av att studera effekterna av substratbuller och inkludera dem i den traditionella designmetoden. ∆Σ analog-till-digital omvandlare är ett perfekt exempel på digital integration i traditionellt analoga kretsar. ADC, som används för att gränssnitta digitala kretsar till en analog värld, är oumbärliga i blandningssignalsystem och är därför en intressant fallstudie. A ∆Σ arkitektur används i denna avhandling för att studera effekterna av substratstörning. En bakgrundsstudie presenteras i avhandlingen för att bättre förstå ∆Σ modulatorer och substratkopplingar. En intensiv teoretisk bakgrund på generering, förökning och mottagande av substratbuller presenteras i ljuset av befintliga undersökningar. Systemoch beteendemodellmodeller föreslås inkludera effekterna av substratbuller i konstruktionsstadiet. Ett maximalt förfall på 10dB ses på grund av injektion av substratbuller på systemnivå medan ett förfall av 12dB ses i beteende simuleringar.En lösning föreslås med hjälp av kontrollerade klockträdfördröjningar för att övervinna effekterna av substratbuller. Lösningen är verifierad på både system och beteendenivåer. De brusmodeller som används för att driva studierna kan vidare användas i blandningssignalsystem för att designa anpassade lösningar.

This paper explores the noise shaping and noise producing qualities of Delta-Sigma Modulators (DSM) and Pulse-Width Modulators (PWM). DSM has long been dominant in the Delta Sigma Analog-to-Digital Converter (DSADC) as a noise-shaped quantizer and time discretizer, while PWM, with a similar self oscillating structure, has seen use in Class D Power Amplifiers, performing a similar function. It has been shown that the PWM in Class D Amplifiers outperforms the DSM [1], but could this advantage be used in DSADC use-cases? LTSpice simulation and printed circuit board implementation and test are used to present data on four variations of these modulators: The DSM, PWM, the out-of-loop discretized PWM (OOLDP), and the cascaded modulator. A generic form of an Nth order loop filter is presented, where three orders of this generic topology are analyzed in simulation for each modulator, and two orders are used in physical testing.

Analog-to-Digital Converters (ADCs) can be classified into two categories namely Nyquist-rate ADCs and OversampledADCs. Nyquist-rate ADCs can process very high bandwidths while Oversampling ADCs provide high resolution using coarse quantizers and support lower input signal bandwidths. This work describes a Reconfigurable ADC (R-ADC) architecture which models 14 different ADCs utilizing four four-bit flash ADCs and four Reconfigurable Blocks (RBs). Both Nyquist-rate and Oversampled ADCs are included in the reconfiguration scheme. The R-ADC supports first- and second-order Sigma-Delta (ΣΔ) ADCs. Cascaded ΣΔ ADCs which provide high resolution while avoiding the stability issues related to higher order ΣΔ loops are also included. Among the Nyquist-rate ADCs, pipelined and time interleaved ADCs are modeled. A four-bit flash ADC with calibration is used as the basic building block for all ADC configurations. The R-ADC needs to support very high sampling rates (1 GHz to 2 GHz). Hence switched-capacitor (SC) based circuits are used for realizing the loop filters in the ΣΔ ADCs. The pipelined ADCs also utilize an SC based block called Multiplying Digital-to-Analog Converter (MDAC). By analyzing the similarities in structure and function of the loop filter and MDAC, a RB has been designed which can accomplish the function of either block based on the selected configuration. Utilizing the same block for various configurations reduces power and area requirements for the R-ADC. In SC based circuits, the minimum sampling capacitance is limited by the thermal noise that can be tolerated in order to achieve a specific ENOB. The thermal noise in a ΣΔ ADC is subjected to noise shaping. This results in reduced thermal noise levels at the inputs of successive loop filters in cascaded or multi-order ΣΔ ADCs. This property can be used to reduce the sampling capacitance of successive stages in cascaded and multi-order ΣΔ ADCs. In pipelined ADCs, the thermal noise in successive stages are reduced due to the inter-stage gain of the MDAC in each stage. Hence scaling of sampling capacitors can be applied along the pipeline stages. The RB utilizes the scaling of capacitor values afforded by the noise shaping property of ΣΔ loops and the inter-stage gain of stages in pipelined ADCs to reduce the total capacitance requirement for the specified Effective Number Of Bits (ENOB). The critical component of the RB is the operational amplifier (opamp). The speed of operation and ENOB for different configurations are determined by the 3 dB frequency and DC gain of the opamp. In order to find the specifications of the opamp, the errors introduced in ΣΔ and pipelined ADCs by the finite gain and bandwidth of the opamp were modeled in Matlab.The gain and bandwidth requirements for the opamp were derived from the simulation results. Unlike Nyquist-rate ADCs, the ΣΔ ADCs suffer from stability issues when the input exceeds a certain level. The maximum usable input level is determined by the resolution of the quantizer and the order of the loop filter in the ΣΔADC. Using Matlab models, the maximum value of input for different oversampling ADC configurations in the R-ADC were found. The results obtained from simulation are comparable to the theoretical values. The cascaded ADCs require digital filter functions which enable the cancellation of quantization noise from certain stages. These functions were implemented in Matlab. For the R-ADC, these filter functions need to run at very high sampling rates. The ΣΔ loop filter transfer functions were chosen such that their coefficients are powers of two, which would allow them to be implemented as shift and add operations instead of multiplications. The R-ADC configurations were simulated in Matlab. A schematic for the R-ADC was developed in Cadence using ideal switches and a finite gain, single-pole operational transconductance amplifier model. The ADC configuration was selected by four external bits. Performance parameters such as SNR, SNDR and SFDR obtained from simulations in Cadence agree with those from Matlab for all ADC configurations.

<p>This thesis demonstrates the high- level modelling and design of oversampled delta- sigma noise shapers for D/A conversion. It presents an overview and study on digital- to- analog converters (DAC) followed by the noise shapers. It helps us to understand how to design a noise shaper model and algorithmic expressions are presented. The models are verified through high level simulations. The usage of models is to reduce the design time and get a good understanding for fundamental limitations on performance. Instead of time consuming circuit- level simulations, we point out the behavioural- level and algorithmic- level simulations of the noise shaper and the entire system comprising of interpolation filter, noise shaper followed by pulse amplitude modulation and reconstruction filtering. We have used the delta- sigma modulators to reduce the number of bits representing the digital signal. It is found that the requirement on oversampled DACs are tough. It is emphasised that the design of an oversampling converter is a filter designproblem. There is a large number of trade- offs that can be made between the different building blocks in the OSDAC.</p>

With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequencysynthesizers. The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.

This thesis demonstrates the high- level modelling and design of oversampled delta- sigma noise shapers for D/A conversion. It presents an overview and study on digital- to- analog converters (DAC) followed by the noise shapers. It helps us to understand how to design a noise shaper model and algorithmic expressions are presented. The models are verified through high level simulations. The usage of models is to reduce the design time and get a good understanding for fundamental limitations on performance. Instead of time consuming circuit- level simulations, we point out the behavioural- level and algorithmic- level simulations of the noise shaper and the entire system comprising of interpolation filter, noise shaper followed by pulse amplitude modulation and reconstruction filtering. We have used the delta- sigma modulators to reduce the number of bits representing the digital signal. It is found that the requirement on oversampled DACs are tough. It is emphasised that the design of an oversampling converter is a filter designproblem. There is a large number of trade- offs that can be made between the different building blocks in the OSDAC.

In this research, a time-based oversampling delta-sigma (ΔΣ) ADC architecture is introduced. This system uses time, rather than voltage or current, as the analog variable for its quantizer, and the noise shaping process is realized by modulating the width of a variable-width digital “pulse.” The ΔΣ loop integrator, the quantizer and digital-to-analog converter (DAC) are all time-based circuits and are implemented using digital gates only. Hence, no amplifier or voltage-based circuit is required. The proposed architecture not only offers a viable for nano-scale ‘digital’ IC technologies, but also enables improved circuit performance compared to the state-of-the-art. This is in contrast to conventional voltage-based analog circuit design, whose performance decreases with scaling due to increasingly higher voltage uncertainty due to supply voltage. The proposed architecture allows all digital implementation after the Voltage to Time Converter (VTC) and merged multi-bit quantizer/DAC blocks by taking advantage of delay lines reusable in both quantization and DAC operation. The novelty of this architecture is digital pulse width processing to implement the ΔΣ modulation. It is realized with small area and potentially can take advantage from the process scaling. A 3-bit prototype of this ADC in 0.18 μm CMOS process is implemented, tested, and presented. With an OSR of 36 and a bandwidth of 2 MHz, it achieves a SNDR of 34.6 dB while consuming 1.5 mA from a 1.8 V supply. The core occupies an area of 0.0275 mm² (110μm × 250μm = 0.0275 mm²). The second generation of the architecture was fabricated in IBM 45 nm SOI process. The oversampling frequency of this system is 705 MHz and oversampling ratio of 64. The expected performance is 7-bit effective resolution for a 5.5 MHz bandwidth while consuming 8mW of power and occupying a core area of less than 0.02 mm² (160μm × 120μm = 0.0192 mm²). / text