Technology scaling beyond Moore’s law demands cutting-edge solutions of the gate length scaling in sub-10 nm regime for low power high speed operations. Recently SOI technology has received considerable attention, however manufacturable solutions in sub-10 nm technologies are not yet known for future nanoelectronics. Therefore, to continue scalinginsub-10 nm region, new one(1D) and two dimensional(2D) “nano-materials” and engineering are expected to keep its pace. However, significant challenges must be overcome for nano-material properties in carrier transport to be useful in future silicon nanotechnology. Thus, it is very important to understand and modulate their electronic band structure and transport properties for low power nanoelectronics applications. This thesis tries to provide solutions for some problems in this area. In recent times, one dimensional Silicon nanowire has emerged as a building block for the next generation nano-electronic devices as it can accommodate multiple gate transistor architecture with excellent electrostatic integrity. However as the experimental study of various energy band parameters at the nanoscale regime is extremely challenging, usually one relies on the atomic level simulations, the results of which are at par with the experimental observations. Two such parameters are the band gap and effective mass, which are of pioneer importance for the understanding of the current transport mechanism. Although there exists a large number of empirical relations of the band gap in relaxed Silicon nanowire, however there is a growing demand for the development of a physics based analytical model to standardize different energy band parameters which particularly demands its application in TCAD software for predicting different electrical characteristics of novel devices and its strained counterpart to increase the device characteristics significantly without changing the device architecture. In the first part of this work reports the analytical modeling of energy band gap and electron transport effective mass of relaxed and strained Silicon nanowires in various crystallographic directions for future nanoelectronics. The technology scaling of gate length in beyond Moore’s law devices also demands the SOI body thickness, TSi0 which is essentially very challenging task in nano-device engineering. To overcome this circumstance, two dimensional crystals in atomically thin layered materials have found great attention for future nanolectronics device applications. Graphene, one layer of Graphite, is such 2D materials which have found potentiality in high speed nanoelectronics applications due to its several unique electronic properties. However, the zero band gap in pure Graphene makes it limited in switching device or transistor applications. Thus, opening and tailoring a band gap has become a highly pursued topic in recent graphene research. The second part of this work reports atomistic simulation based real and complex band structure properties Graphene-Boron nitride heterobilayer and Boron Nitride embedded Graphene nanoribbons which can improve the grapheme and its nanoribbon band structure properties without changing their originality. This part also reports the direct band-to-band tunneling phenomena through the complex band structures and their applications in tunnel field effect transistors(TFETs) which has emerged as a strong candidate for next generation low-stand by power(LSTP) applications due to its sub-60mV/dec Sub threshold slope(SS). As the direct band-to-band tunneling(BTBT) is improbable in Silicon(either its bulk or nanowire form), it is difficult to achieve superior TFET characteristics(i.e., very low SS and high ON cur-rent) from the Silicon TFETs. Whereas, it is explored that much high ON current and very low subthreshold slope in hybrid Graphene based TFET characteristics open a new prospect in future TFETs. The investigations on ultrathin body materials also call for a need to explore new 2D materials with finite band gap and their various nanostructures for future nanoelectronic applications in order to replace conventional Silicon. In the third part of this report, we have investigated the electronic and dielectric properties of semiconducting layered Transition metal dichalcogenide materials (MX2)(M=Mo, W;X =S, Se, Te) which has recently emerged as a promising alternative to Si as channel materials for CMOS devices. Five layered MX2 materials(exceptWTe2)in their 2D sheet and 1D nanoribbon forms are considered to study the real and imaginary band structure of thoseMX2 materials by atomistic simulations. Studying the complex dispersion properties, it is shown that all the five MX2 support direct BTBT in their monolayer sheet forms and offer an average ON current and subthresholdslopeof150 A/mand4 mV/dec, respectively. However, onlytheMoTe2 support direct BTBT in its nanoribbon form, whereas the direct BTBT possibility in MoS2 and MoSe2 depends on the number of layers or applied uniaxial strain. WX2 nanoribbons are shown to be non-suitable for efficient TFET operation. Reasonably high tunneling current in these MX2 shows that these can take advantage over conventional Silicon in future tunnel field effect transistor applications.

Technology scaling beyond Moore’s law demands cutting-edge solutions of the gate length scaling in sub-10 nm regime for low power high speed operations. Recently SOI technology has received considerable attention, however manufacturable solutions in sub-10 nm technologies are not yet known for future nanoelectronics. Therefore, to continue scalinginsub-10 nm region, new one(1D) and two dimensional(2D) “nano-materials” and engineering are expected to keep its pace. However, significant challenges must be overcome for nano-material properties in carrier transport to be useful in future silicon nanotechnology. Thus, it is very important to understand and modulate their electronic band structure and transport properties for low power nanoelectronics applications. This thesis tries to provide solutions for some problems in this area. In recent times, one dimensional Silicon nanowire has emerged as a building block for the next generation nano-electronic devices as it can accommodate multiple gate transistor architecture with excellent electrostatic integrity. However as the experimental study of various energy band parameters at the nanoscale regime is extremely challenging, usually one relies on the atomic level simulations, the results of which are at par with the experimental observations. Two such parameters are the band gap and effective mass, which are of pioneer importance for the understanding of the current transport mechanism. Although there exists a large number of empirical relations of the band gap in relaxed Silicon nanowire, however there is a growing demand for the development of a physics based analytical model to standardize different energy band parameters which particularly demands its application in TCAD software for predicting different electrical characteristics of novel devices and its strained counterpart to increase the device characteristics significantly without changing the device architecture. In the first part of this work reports the analytical modeling of energy band gap and electron transport effective mass of relaxed and strained Silicon nanowires in various crystallographic directions for future nanoelectronics. The technology scaling of gate length in beyond Moore’s law devices also demands the SOI body thickness, TSi0 which is essentially very challenging task in nano-device engineering. To overcome this circumstance, two dimensional crystals in atomically thin layered materials have found great attention for future nanolectronics device applications. Graphene, one layer of Graphite, is such 2D materials which have found potentiality in high speed nanoelectronics applications due to its several unique electronic properties. However, the zero band gap in pure Graphene makes it limited in switching device or transistor applications. Thus, opening and tailoring a band gap has become a highly pursued topic in recent graphene research. The second part of this work reports atomistic simulation based real and complex band structure properties Graphene-Boron nitride heterobilayer and Boron Nitride embedded Graphene nanoribbons which can improve the grapheme and its nanoribbon band structure properties without changing their originality. This part also reports the direct band-to-band tunneling phenomena through the complex band structures and their applications in tunnel field effect transistors(TFETs) which has emerged as a strong candidate for next generation low-stand by power(LSTP) applications due to its sub-60mV/dec Sub threshold slope(SS). As the direct band-to-band tunneling(BTBT) is improbable in Silicon(either its bulk or nanowire form), it is difficult to achieve superior TFET characteristics(i.e., very low SS and high ON cur-rent) from the Silicon TFETs. Whereas, it is explored that much high ON current and very low subthreshold slope in hybrid Graphene based TFET characteristics open a new prospect in future TFETs. The investigations on ultrathin body materials also call for a need to explore new 2D materials with finite band gap and their various nanostructures for future nanoelectronic applications in order to replace conventional Silicon. In the third part of this report, we have investigated the electronic and dielectric properties of semiconducting layered Transition metal dichalcogenide materials (MX2)(M=Mo, W;X =S, Se, Te) which has recently emerged as a promising alternative to Si as channel materials for CMOS devices. Five layered MX2 materials(exceptWTe2)in their 2D sheet and 1D nanoribbon forms are considered to study the real and imaginary band structure of thoseMX2 materials by atomistic simulations. Studying the complex dispersion properties, it is shown that all the five MX2 support direct BTBT in their monolayer sheet forms and offer an average ON current and subthresholdslopeof150 A/mand4 mV/dec, respectively. However, onlytheMoTe2 support direct BTBT in its nanoribbon form, whereas the direct BTBT possibility in MoS2 and MoSe2 depends on the number of layers or applied uniaxial strain. WX2 nanoribbons are shown to be non-suitable for efficient TFET operation. Reasonably high tunneling current in these MX2 shows that these can take advantage over conventional Silicon in future tunnel field effect transistor applications.

<div>The work involves two new method implementation and application in the Quantum transport community for nano-scale electronic devices. </div><div><br></div><div>First method: Ab-initio Tight-Binding(TB)</div><div> </div><div>As the surfacing of novel 2D materials, layers can be stacked freely on top of each other bound by Van der Waals force with atomic precision. New devices created with unique characteristics will need the theoretical guidance. The empirical tight-binding method is known to have difficulty accurately representing Hamiltonian of the 2D materials. Maximally localized Wannier function(MLWF) constructed directly from ab-initio calculation is an efficient and accurate method for basis construction. Together with NEGF, device calculation can be conducted. The implementation of MLWF in NEMO5 and the application on 2D MOS structure to demystify interlayer coupling are addressed. </div><div> </div><div>Second method: Büttiker-probe Recombination/Generation(RG) method:</div><div><br></div><div>The non-equilibrium Green function (NEGF) method is capable of nanodevice performance predictions including coherent and incoherent effects. To treat incoherent scattering, carrier generation and recombination is computationally very expensive. In this work, the numerically efficient Büttiker-probe model is expanded to cover recombination and generation effects in addition to various incoherent scattering processes. The capability of the new method to predict nanodevices is exemplified with quantum well III-N light-emitting diodes and photo-detector. Comparison is made with the state of art drift-diffusion method. Agreements are found to justify the method and disagreements are identified attributing to quantum effects. </div><div><br></div><div>The two menthod are individually developed and utilized together to study BP/MoS2 interface. In this vertical 2D device, anti-ambipolar(AAP) IV curve has been identified experimentally with different explanation in the current literature. An atomistic simulation is performed with basis generated from density functional theory. Recombination process is included and is able to explain the experiment findings and to provide insights into 2D interface devices.</div><div><br></div><div> </div>

Like cell to the human body, transistors are the basic building blocks of any electronics circuits. Silicon has been the industries obvious choice for making transistors. Transistors with large size occupy large chip area, consume lots of power and the number of functionalities will be limited due to area constraints. Thus to make the devices smaller, smarter and faster, the transistors are aggressively scaled down in each generation. Moore's law states that the transistors count in any electronic circuits doubles every 18 months. Following this Moore's law, the transistor has already been scaled down to 14 nm. However there are limitations to how much further these transistors can be scaled down. Particularly below 10 nm, these silicon based transistors hit the fundamental limits like loss of gate control, high leakage and various other short channel effects. Thus it is not possible to favor the silicon transistors for future electronics applications. As a result, the research has shifted to new device concepts and device materials alternative to silicon. Carbon is the next abundant element found in the Earth and one of such carbon based nanomaterial is graphene. Graphene when extracted from Graphite, the same material used as the lid in pencil, have a tremendous potential to take future electronics devices to new heights in terms of size, cost and efficiency. Thus after its first experimental discovery of graphene in 2004, graphene has been the leading research area for both academics as well as industries. This dissertation is focused on the analysis and optimization of graphene based circuits for future electronics. The first part of this dissertation considers graphene based transistors for analog/radio frequency (RF) circuits. In this section, a dual gate Graphene Field Effect Transistor (GFET) is considered to build the case study circuits like voltage controlled oscillator (VCO) and low noise amplifier (LNA). The behavioral model of the transistor is modeled in different tools: well accepted EDA (electronic design automation) and a non-EDA based tool i.e. \simscape. This section of the dissertation addresses the application of non-EDA based concepts for the analysis of new device concepts, taking LC-VCO and LNA as a case study circuits. The non-EDA based approach is very handy for a new device material when the concept is not matured and the model files are not readily available from the fab. The results matches very well with that of the EDA tools. The second part of the section considers application of multiswarm optimization (MSO) in an EDA tool to explore the design space for the design of LC-VCO. The VCO provides an oscillation frequency at 2.85 GHz, with phase noise of less than -80 dBc/Hz and power dissipation less than 16 mW. The second part of this dissertation considers graphene nanotube field effect transistors (GNRFET) for the application of digital domain. As a case study, static random access memory (SRAM) hs been design and the results shows a very promising future for GNRFET based SRAM as compared to silicon based transistor SRAM. The power comparison between the two shows that GNRFET based SRAM are 93% more power efficient than the silicon transistor based SRAM at 45 nm. In summary, the dissertation is to expected to aid the state of the art in following ways: 1) A non-EDA based tool has been used to characterize the device and measure the circuit performance. The results well matches to that obtained from the EDA tools. This tool becomes very handy for new device concepts when the simulation needs to be fast and accuracy can be tradeoff with. 2)Since an analog domain lacks well-design design paradigm, as compared to digital domain, this dissertation considers case study circuits to design the circuits and apply optimization. 3) Performance comparison of GNRFET based SRAM to the conventional silicon based SRAM shows that with maturation of the fabrication technology, graphene can be very useful for digital circuits as well.

<p>Most work on amplifier linearity has focused on the transconductance (gm) linearity, but there is increasing evidence that the voltage-dependence of the gate-source capacitance (Cgs) plays an important role in the linearity of emerging devices. This work addresses the capacitance contribution by incorporating the nonlinearities attributed to the voltage dependency of Cgs of a general FET on a circuit-level Cg amplifier model.</p> <p>An amplifier model including a voltage-dependent Cgs, and a voltage-dependent gm is studied using harmonic analysis and Volterra series. A closed form expression for the  third-order intercept point (IP3) of the amplifier, which depends on the nonlinear coefficients of Cgs, is obtained. A simple design rule, and a formula for the reduction of the IP3 due to the voltage-dependent Cgs are also presented. </p> <p>As application examples, the linearity of an amplifier based on a specific device is analyzed for two cases by extracting the nonlinear circuit parameters of the device. First for an analytic model of a bulk mosfet. Second for a one-dimensional, ballistic, coaxially gated Si nanowire. For low frequencies of design, the distortion introduced by gm is predominant, but for high frequencies it is obscured by the distortion coming from Cgs.</p> <p>We conclude that taking into account the voltage-dependence of Cgs is crucial when predicting the linearity behavior of a Cg amplifier, either designed for high-frequency operation, or based on a device operating near the quantum capacitance limit. </p>

<p>The recent groundbreaking demonstrations of quantum supremacy in noisy intermediate scale quantum (NISQ) computing era has triggered an intense activity in establishing finer boundaries between classical and quantum computing. In this dissertation, we use established techniques based on quantum Monte Carlo (QMC) to map quantum problems into probabilistic networks where the fundamental unit of computation, p-bit, is inherently probabilistic and can be tuned to fluctuate between ‘0’ and ‘1’ with desired probability. We can view this mapped network as a Boltzmann machine whose states each represent a Feynman path leading from an initial configuration of q-bits to a final configuration. Each such path, in general, has a complex amplitude, ψ which can be associated with a complex energy. The real part of this energy can be used to generate samples of Feynman paths in the usual way, while the imaginary part is accounted for by treating the samples as complex entities, unlike ordinary Boltzmann machines where samples are positive. This mapping of a quantum circuit onto a Boltzmann machine with complex energies should be particularly useful in view of the advent of special-purpose hardware accelerators known as Ising Machines which can obtain a very large number of samples per second through massively parallel operation. We also demonstrate this acceleration using a recently used quantum problem and speeding its QMC simulation by a factor of ∼ 1000× compared to a highly optimized CPU program. Although this speed-up has been demonstrated using a graph colored architecture in FPGA, we project another ∼ 100× improvement with an architecture that utilizes clockless analog circuits. We believe that this will contribute significantly to the growing efforts to push the boundaries of the simulability of quantum circuits with classical/probabilistic resources and comparing them with NISQ-era quantum computers. </p>

The absorptance in vertical nanowire (nw) arrays is typically dominated by three optical phenomena: radial mode resonances, near-field evanescent wave coupling, and Fabry–Perot (F-P) mode resonances. The contribution of these optical phenomena to GaAs, InP and InAs nw absorptance was simulated using the finite element method. The study compared the absorptance between finite and semi-infinite nws with varying geometrical parameters, including the nw diameter (D), array period (P), and nw length (L). Simulation results showed that the resonance peak wavelength of the HE1n radial modes linearly red-shifted with increasing D. The absorptance and spectral width of the resonance peaks increased as L increased, with an absorptance plateau for very long nws that depended on D and P. Near-field coupling between neighbouring nanowires (nws) was observed to increase with increasing diameter to period ratio (D/P). The effect of F-P modes was more pronounced for shorter nws and weakly coupled light. Based on the collective observation of the correlation between nw geometry and optical phenomena in GaAs, InP, and InAs nw arrays, a periodic array of vertical InSb nws was designed for photodetectors in the low-atmospheric absorption window (λ = 3-5 μm) within the mid-wavelength infrared (MWIR) spectrum (λ = 3-8 μm). Simulations, using the finite element method, were implemented to optimize the nw array geometrical parameters (D, P, and L) for high optical absorptance (~0.8), which exceeded that of a thin film of equal thickness. The results further showed that the HE1n resonance wavelengths in InSb nw arrays can be tuned by adjusting D and P, thus enabling multispectral absorption throughout the near infrared (NIR) to MWIR region. Optical absorptance was investigated for a practical photodetector consisting of a vertical InSb nw array embedded in bisbenzocyclobutene (BCB) as a support layer for an ultrathin Ni contact layer. Polarization sensitivity of the photodetector was examined. Lastly, how light flux enters the nw top and sidewalls on HE11 resonance was investigated. / Dissertation / Doctor of Philosophy (PhD)

<div> <div> <p>Phase transition materials (PTM) have garnered immense interest in concurrent post-CMOS electronics, due to their unique properties such as - electrically driven abrupt resistance switching, hysteresis, and high selectivity. The phase transitions can be attributed to diverse material-specific phenomena, including- correlated electrons, filamentary ion diffusion, and dimerization. In this research, we explore the application space for these materials through extensive device-circuit co-design and propose new ideas harnessing their unique electrical properties. The abrupt transitions and high selectivity of PTMs enable steep (< 60 mV/decade) switching characteristics in Hyper-FET, a promising post-CMOS transistor. We explore device-circuit co-design methodology for Hyper-FET and identify the criterion for material down-selection. We evaluate the achievable voltage swing, energy-delay trade-off, and noise response for this novel device. In addition to the application in low power logic device, PTMs can actively facilitate non-volatile memory design. We propose a PTM augmented Spin Transfer Torque (STT) MRAM that utilizes selective phase transitions to boost the sense margin and stability of stored data, simultaneously. We show that such selective transitions can also be used to improve other MRAM designs with separate read/write paths, avoiding the possibility of read-write conflicts. Further, we analyze the application of PTMs as selectors in cross-point memories. We establish a general simulation framework for cross-point memory array with PTM based <i>selector</i>. We explore the biasing constraints, develop detailed design methodology, and deduce figures of merit for PTM selectors. We also develop a computationally efficient compact model to estimate the leakage through the sneak paths in a cross-point array. Subsequently, we present a new sense amplifier design utilizing PTM, which offers built-in tunable reference with low power and area demand. Finally, we show that the hysteretic characteristics of unipolar PTMs can be utilized to achieve highly efficient rectification. We validate the idea by demonstrating significant design improvements in a <i>Cockcroft-Walton Multiplier, </i>implemented with TS based rectifiers. We emphasize the need to explore other PTMs with high endurance, thermal stability, and faster switching to enable many more innovative applications in the future.</p></div></div>

Ce travail de thèse porte sur l'application des techniques Scanning Capacitance Microscopy (SCM) et Scanning Spreading Resistance Microscopy (SSRM) pour la caractérisation électrique de nanofils de ZnO avec l'objectif d'en déterminer le dopage par profilage des porteurs libres suite à des essais de dopage de type p. Afin de pouvoir utiliser un référentiel planaire nécessaire à ces mesures par sonde locale, un procédé de remplissage par dip-coating et de polissage a été spécialement développé sur des champs de nanofils quasi-verticaux. De plus, dans le but de parvenir à un étalonnage des mesures SCM et SSRM, nous avons conçu et fait fabriquer des échantillons étalons de dopage de type n, contenant des niveaux de Ga en escalier de densité variable de 2×10^17 à 3×10^20 cm^-3. Les mesures sur des coupes transversales de ces deux de structures multicouches ont permis, pour la première fois sur ZnO d'établir un étalonnage des mesures SCM et SSRM et de déterminer le dopage intrinsèque électriquement actif de couches 2D nanométriques, résultat difficilement atteignable par d'autres techniques d'analyse. Des résultats inattendus de concentration résiduelle de porteur de l'ordre de 2×10^18 et 3×10^18 cm^-3 ont été trouvés sur les nanofils de ZnO crus par MOCVD et par CBD respectivement. Outre la caractérisation électrique microscopique des nanofils par SCM et SSRM, des techniques macroscopiques classiques ont été utilisées pour caractériser des assemblées importantes de nanofils de ZnO. L'origine de la difference entre les résultats de deux genres de technique a été discutée. Nous avons aussi étudié les effets des dopages ex-situ par diffusion du phosphore (procédé SOD) et des dopages in situ par incorporation d'antimoine (Sb) pendant la croissance MOCVD. Les résultats majeurs sont obtenus pour l'antimoine, en utilisant des couches ZnO: Sb 2D et des nanofils cœur-coquille ZnO/ZnO: Sb, ou l'hypothèse d'une compensation partielle du dopage n résiduel par un centre accepteur créé par le dopage Sb semble pouvoir être établie raisonnablement. / Based on atomic force microscope (AFM), scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) have demonstrated high efficiency for two dimensional (2D) electrical characterizations of Si semiconductors at nanoscale and then have been extensively employed in Si-based structures/devices before being extended to the study of some other semiconductor materials. However, ZnO, a representative of the third generation semiconductor material, being considered a promising candidate for future devices in many areas, especially in opto-electronic area, has rarely been addressed. Recently, extensive research interests have been attracted by ZnO NWs for future devices such as LED, UV laser and sensor. Therefore, a good understanding of electrical properties of the NWs is in need. In this context, this thesis work is dedicated to the 2D electrical characterization of ZnO NWs with the focus of carrier profiling on this kind of nanostructure in the effort of their p-type doping. For this purpose, a planarization process has been developed for the NWs structure in order to obtain an appropriate sample surface and perform SCM/SSRM measurements on the top of the NWs. For quantitative analysis, Ga doped ZnO multilayer staircase structures were developed serving as calibration samples. Finally, residual carrier concentrations inside the CBD and MOCVD grown ZnO NWs are determined to be around 3×10^18 cm^-3 and 2×10^18 cm^-3, respectively. The results from SCM/SSRM characterization have been compared with that from macroscopic C-V measurements on collective ZnO NWs and the differences are discussed. In addition to carrier profiling on NWs structure, applications of SCM/SSRM on some other ZnO-based nanostructures are also investigated including ZnO:Sb films, ZnO/ZnO:Sb core-shell NWs structure, ZnO/ZnMgO core-multishell coaxial heterostructures.

L'intégration de diélectriques High-k dans les empilements de grille des dispositifs MOS a fait naître de nouvelles interrogations concernant la fiabilité des futurs nœuds technologiques. La miniaturisation constante des dispositifs conduisant à l'amincissement des épaisseurs d'oxyde de grille, leur caractérisation électrique est rendue de plus en plus complexe à l'échelle du dispositif. Pour palier à ce problème, l'utilisation d'un microscope à force atomique en mode conducteur sous ultravide permet grâce à la faible surface de contact entre la pointe et l'échantillon de réduire suffisamment le courant tunnel pour pouvoir étudier la dégradation et le claquage diélectrique d'oxyde ultra fin. La comparaison systématique des résultats de fiabilité de l'empilement High-k du nœud 28nm et de la couche interfaciale seule ayant subi les mêmes étapes de développement que celles présentes dans l'empilement, obtenus par C-AFM sous ultra vide, ont permis de montrer expérimentalement que la probabilité de claquage des oxydes de grille High-k est gouvernée par la fiabilité propre des couches qui la composent, et de déduire une loi d'extrapolation de la durée de vie en tension et en surface ce qui permet de prédire la statistique de défaillance du dispositif. Les impacts d'un pré-stress en tension de l'ordre de la milliseconde sur les distributions de claquage des oxydes de grille simples et bicouches ont été rapportés. Ces résultats sont expliqués dans ce manuscrit par le déclenchement lors de l'application du stress, d'une dégradation au sein de l'oxyde, prenant naissance dans la couche interfaciale des oxydes High-k et conduisant à une réduction locale de l'épaisseur de diélectrique. Des phénomènes de résistance différentielle négative au moment de la rupture diélectrique ont été étudiés et modélisés pour différentes épaisseurs d'oxyde, par une croissance filamentaire de la dégradation. Il a été possible de donner une expression analytique reliant le temps caractéristique de croissance filamentaire et le temps moyen de claquage observé sur les distributions statistiques. Enfin, les mesures C-AFM de ce travail ont été étendues au cas des structures MIM utilisées pour le développement des futurs mémoires résistives OxRAM. Dans ce cas un effet d'auto-guérison à l'échelle nanométrique a été mis en évidence. / Integration of High-k dielectrics in gate oxides of MOS raised new issues concerning the reliability of futur technology nodes. The constant miniaturisation of devices leads to thinner gate oxides, making their electrical caracterisation more complex at the device scale. To solve this problem, an atomic force microscope in conductive mode under ultra high vacuum can be used thanks to the readuce contact area between the tip and the sample which allow a drastic decrease of the tunneling current and thus the study of the degradation and the dielectric breakdown of ultra-thin oxides. The systematic comparaison of the TDDB distributions obtained on the High-k gate oxide of the 28nm technology node on one side and obtained on the Interfacial layer alone revealed that the failure probability of High-k oxides is governed by the failure probability of each layer present in the stack. This allow to give an extrapolation law of the High-k gate oxide lifetime as a function of the applied voltage and the electrode area and to predict the failure statistic of the 28nm tehcnology node. The impact of voltage pre-stress with a microseconde range of duration on the TDDB and VBD distributions of both single layer and High-k gate oxides is given is the manuscript. The results are then interpreted by an invasive degradation nucleating from an interface during a stress and leading to a local thinned oxide. Pre-breakdown negative differential resistance have been studied and modeled for several oxide thickness, using a growing mecanism of the elctrical degradation. An analytic expression linking the growth caracteristic time of the filament and the mean time to breakdown observed on the statistical distributions has then been given. Finally, C-AFM measurements developped in this work has been extended to MIM structures used for oxide resistive random access memories (OxRAM). A self healing has been observed at the nanometric scale for these samples.