Wireless Sensor Networks (WSNs) are popular for their wide scope of application domains ranging from agricultural, medical, defense, industrial, social, mining, etc. Many of these applications are in outdoor type environments that are unregulated and unpredictable, thus, potentially hostile or physically harsh for sensors. The popularity of WSNs stems from their fundamental concept of being low cost and ultra-low power wireless devices that can monitor and report sensor readings with little user intervention, which has led to greater demand for WSN deployment in harsh industrial environments. We argue that there are a new set of architectural challenges and requirements imposed on the hardware, software, and network architecture of a wireless sensor platform to operate effectively under harsh industrial environments, which are not met by currently available WSN platforms. We propose a new sensor platform, called Sprouts. Sprouts is a readily deployable, physically rugged, volumetrically miniature, modular, network standard, plug-and-play (PnP), and easy to use sensor platform that will assist university researchers, developers, and industrial companies to evaluate WSN applications in the field, and potentially bring about new application domains that were previously difficult to accomplish using off the shelf WSN development platforms. Therefore, we addresses the inherent requirements and challenges across the hardware, software, and network layer required for designing and implementing Sprouts sensor platform for harsh industrial environments. We fully implement the hardware, network, and software architecture for the Sprouts platform and verify that they meet the requirements for harsh environments. We deploy the Sprouts platform customized with our PnP ultrasound sensor module in an industrial application to monitor the health conditions of Syncrude's vibration screens operating under extreme harsh conditions. Sprouts has been showcased in OCE Discovery 2011, and has been proven to be extremely valuable for industrial mining companies such as Syncrude. / Thesis (Ph.D, Computing) -- Queen's University, 2013-09-28 16:14:48.223

Avec la croissance actuelle du marché des applications de transfert de données multimédia à très haut débit, les bandes de fréquences autour de 60 GHz sont une nouvelle alternative promettant des performances intéressantes en terme de débits mais soulèvent des défis techniques et technologiques au niveau des architectures et circuits. C'est dans ce cadre que s'inscrit cette thèse, qui propose une approche multi bande impulsionnelle MBOOK avec un récepteur à détection d'énergie, et qui analyse plus spécifiquement les verrous au niveau de l'émetteur. L'étude du canal de propagation à 60 GHz, basée sur les modèles de canaux du standard IEEE 802.15.3c, a permis de démontrer la potentialité de cette architecture et permet d'atteindre des débits de 2 Gbps à 2metres dans un environnement de type résidentiel. Le dimensionnement de l'architecture ainsi que des performances des principaux blocs ont conduit à plusieurs possibilités pour l'architecture de l'émetteur MBOOK à 60 GHz. Les critères ont été d'assurer un compromis performances, consommation. Une étude approfondie sur l'étude des imperfections de certains blocs critiques et l'impact sur l'impulsion transmise, et donc sur les performances du système ont été établies. Le banc de filtres, nécessaire à l'émission et à la réception, représente l'un des verrous, et nous proposons une solution de filtrage à base de lignes couplées. L'étude des solutions de génération d'impulsions, des étages de commutation, et des étages d'amplification de l'émetteur sont détaillées et discutées dans les deux derniers chapitres / With the current increasing market request concerning high speed data rates applications, the 60 GHz frequency bands seems to be one of the new promising alternatives for high data rate wireless communications. In this context, the development of new systems operating at these frequencies becomes a very attractive research subject. This study focuses on nomadic systems offering high data and reconfigurable rates, low complexity, low power consumption for short communications. One of the important tasks in the millimetre wave architecture design is to consider the channel propagation characteristics simultaneously with the technological performance of integrated circuits and antennas. This requires a co-design of the entire system. Therefore, we begun by studying the characteristics of the channel propagation channel at 60GHz according to the IEEE 802.15.3c and IEEE 802.11.ad models. This PHD thesis proposes a new transceiver architecture based on multi-band impulse mode, with On Off Keying modulation schema and non coherent receiver. This architecture is dedicated to nomadic systems offering high data and reconfigurable rates, low complexity, low power consumption for short communications. Analysis and performances for the proposed architecture are presented. More than 2 Gbps at 2 m are obtained. The imperfections of some critical blocks and their impact on the transmitted pulses were analysed and thus the performance of the system has been established. The potentiality of microstrip band pass filter bank presenting a constant relative bandwidth and reasonable insertion losses is presented in this study. The study of pulse generation solutions, switchers, amplification stages and antennas are detailed and discussed in the last two chaptersconstant relative bandwidth and reasonable insertion losses is presented in this study.The study of pulse generation solutions, switchers, amplification stages and antennas are detailed and discussed in the last two chapters.

<p>Master thesis work at ITN (Department of Science and Technology) in the areas of A/D-construction and RF-circuit design. Major goal of project were to research suitable possibilities for implementations of direct conversion in transceivers operating in the 160MHz band, theoretic study followed by development of components in the construction environment Cadence. Suitable A/D- converter and other important parts were selected at the end of the theoretic study. Subsampling technique was applied to make A/D sample requirements more realistic to achieve. Besides lowering requirements on A/D-converter it allows a more simple construction, which saves more components than subsampling adds. Subsampling add extra noise, because of that an A/D-converter based on the RSD algorithm was chosen to improve error rate. To achieve high bit-processing rate compared to the used number of transistors, pipeline structure were selected as conversion method. The receiver was that part which gained largest attention because it’s the part which is most interesting to optimise. A/D-conversion is more difficult to construct than D/A conversion, besides there’s more to gain from eliminating mixers in the receiver than in the transmitter.</p>

<p>This report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm.</p><p>The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF).</p><p>The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project.</p><p>A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa.</p><p>When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s.</p><p>The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.</p>

Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart from being capable of handling a wide range of data rates, the transceivers should have low power consumption (mW/Gbps) and be fully integrated. This work discusses enabling techniques to implement such transceivers. Specifically, three designs: (1) a 0.5-4 Gbps serial link which uses current recycling to reduce power dissipation and (2) a 0.5-2.5 Gbps reference-less clock and data recovery circuit which uses a novel frequency detector to achieve unlimited acquisition range and (3) a 2-4 Gbps low power receiver architecture capable of resolving multiple signalling formats with a simplified XOR based phase rotating PLL will be presented. All the three circuit topologies are highly digital and aim to address the requirements of wide operating range, low power dissipation while being fully integrated. Measured results obtained from the prototypes illustrate the effectiveness of the proposed design techniques. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from Dec. 2, 2011 - June 2, 2012

This dissertation presents the design and implementation of circuits and transceivers in CMOS technology to enable many new millimeter-wave applications. A simple approach is presented for accurately modeling the millimeter-wave characteristics of transistors that are not fully captured by contemporary parasitic extraction techniques. Next, the integration of a low-power 60-GHz CMOS on-off keying (OOK) receiver in 90-nm CMOS for use in multi-gigabit per second wireless communications is demonstrated. The use of non-coherent OOK demodulation by a novel demodulator enabled a data throughput of 3.5 Gbps and resulted in the lowest power budget (31pJ/bit) for integrated 60-GHz CMOS OOK receivers at the time of publication. Also presented is the design of a high-power, high-efficiency 45-GHz VCO in 45-nm SOI CMOS. The design is a class-E power amplifier placed in a positive feedback configuration. This circuit achieves the highest reported output power (8.2 dBm) and efficiency (15.64%) to date for monolithic silicon-based millimeter-wave VCOs. Results are provided for the standalone VCO as well as after packaging in a liquid crystal polymer (LCP) substrate. In addition, a high-power high-efficiency (5.2 dBm/6.1%) injection locked oscillator is presented. Finally, the design of a 2-channel 45-GHz vector modulator in 45-nm SOI CMOS for LINC transmitters is presented. A zero-power passive IQ generation network and a low-power Gilbert cell modulator are used to enable continuous 360° vector generation. The IC is packaged with a Wilkinson power combiner on LCP and driven by external DACs to demonstrate the first ever 16-QAM generated by outphasing modulation in CMOS in the Q-band.

Design techniques and procedures to improve performances of radio-frequency and millimeter-wave front-end integrated circuits were developed. Power amplifiers for high data-rate wireless communication applications were designed using CMOS technology employing a novel device resizing and concurrent power-combining technique to implement a multi-mode operation. Comprehensive analysis on the efficiency degradation effect of multi-input-single-output combining transformers with idle input terminals was performed. The proposed discrete resizing and power-combining technique effectively enhanced the efficiency of a linear CMOS power amplifier at back-off power levels. In addition, a novel power-combining transformer that is suitable to generate multi-watt-level output power was proposed and implemented. Employing the proposed power-combining transformer, a high-power linear CMOS power amplifier was designed. Furthermore, receiver building blocks such as a low-noise amplifier, a down-conversion mixer, and a passive balun were implemented using SiGe technology for W-band applications.

This thesis describes the specification, design and implementation of a software-defined radio system on a two-channel 14-bit digitizer/generator. The multi-stage interpolations and decimations which are required to operate two analog-to-digital converters at 800 megasamples per second (MSps) and two digital-to-analog converters at 1600 MSps from a 25 MSps software-side interface, were designed and implemented. Quadrature processing was used throughout the system, and a combination of fine-tunable low-rate mixers and coarse high-rate mixers were implemented to allow frequency translation across the entire first Nyquist band of the converters. Various reconstruction filter designs for the transmitter side were investigated and a cheap implementation was done through the use of programmable base-band filters and polynomial approximation.

Master thesis work at ITN (Department of Science and Technology) in the areas of A/D-construction and RF-circuit design. Major goal of project were to research suitable possibilities for implementations of direct conversion in transceivers operating in the 160MHz band, theoretic study followed by development of components in the construction environment Cadence. Suitable A/D- converter and other important parts were selected at the end of the theoretic study. Subsampling technique was applied to make A/D sample requirements more realistic to achieve. Besides lowering requirements on A/D-converter it allows a more simple construction, which saves more components than subsampling adds. Subsampling add extra noise, because of that an A/D-converter based on the RSD algorithm was chosen to improve error rate. To achieve high bit-processing rate compared to the used number of transistors, pipeline structure were selected as conversion method. The receiver was that part which gained largest attention because it’s the part which is most interesting to optimise. A/D-conversion is more difficult to construct than D/A conversion, besides there’s more to gain from eliminating mixers in the receiver than in the transmitter.

This report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm. The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF). The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project. A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa. When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s. The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.