Les travaux de recherche présentés dans cette thèse consistent principalement en la conception de fonctions intégrées radiofréquences BiCMOS SiGe exploitant des résonateurs à ondes acoustiques de volume FBAR. Contrairement aux techniques actuelles rencontrées dans l'industrie qui consistent à réaliser des filtres et des résonateurs discrets et à les associer par la suite avec les circuits actifs des émetteurs-récepteurs au niveau du boîtier, nos résonateurs sont directement réalisés sur le substrat silicium des circuits actifs RF par une technique appelée intégration " above-IC ". Avec cette méthode d'intégration, les parasites et la modélisation associés aux microsoudures (Wire Bonding) sont éliminés. Elle permet aussi de se passer des circuits d'interface et d'adaptation nécessaires dans le cas de filtres RF discrets. Ceci permet de réduire considérablement la consommation et le volume des systèmes. Des amplificateurs faible bruit filtrants et des oscillateurs visant le standard WLAN IEEE 802.11a ont ainsi été implantés en utilisant cette technique d'intégration "above IC". Les circuits obtenus sont très compacts, et leurs performances, notamment celles des oscillateurs, sont à l'état de l'art. Par ailleurs, des amplificateurs faible bruit et des VCO LC SiGe intégrés pour application WLAN 5GHz sont également présentés et leurs techniques d'optimisation sont données.

The research conducted in this dissertation studies the issues regarding the improvement of phase noise performance in a BiCMOS Silicon Germanium (SiGe) cross-coupled differential-pair voltage controlled oscillator (VCO) in a narrowband application as a result of a tail-current shaping technique. With this technique, low-frequency noise components are reduced by increasing the signal amplitude without consuming additional power, and its effect on overall phase noise performance is evaluated. The research investigates effects of the tail-current as a main contributor to phase noise, and also other effects that may influence the phase noise performance like inductor geometry and placement, transistor sizing, and the gain of the oscillator. The hypothesis is verified through design in a standard 0.35 μm BiCMOS process supplied by Austriamicrosystems (AMS). Several VCOs are fabricated on-chip to serve for a comparison and verify that the employment of tail-current shaping does improve phase noise performance. The results are then compared with mathematical models and simulated results, to confirm the hypothesis. Simulation results provided a 3.3 dBc/Hz improvement from -105.3 dBc/Hz to -108.6 dBc/Hz at a 1 MHz offset frequency from the 5 GHz carrier when employing tail-current shaping. The relatively small increase in VCO phase noise performance translates in higher modulation accuracy when used in a transceiver, therefore this increase can be regarded as significant. Parametric analysis provided an additional 1.8 dBc/Hz performance enhancement in phase noise that can be investigated in future works. The power consumption of the simulated VCO is around 6 mW and 4.1 mW for the measured prototype. The circuitry occupies 2.1 mm2 of die area. Copyright / Dissertation (MEng)--University of Pretoria, 2010. / Electrical, Electronic and Computer Engineering / unrestricted

This paper presents a brief study of the two most commonly used topologies - segmented and traveling-wave - for realizing monolithically integrated electro-optical transmitters consisting of Si-photonics Mach-Zehnder modulators and their electrical drivers. To this end, two new transmitters employing high swing breakdown voltage doubler drivers were designed in the aforementioned topologies and compared with regard to their extinction ratio and DC power consumption at the data rate of 30 Gb/s. It is shown that for the targeted data rate and extinction ratio, a considerably lower power consumption can be achieved with the traveling-wave topology than with its segmented counterpart. The transmitters were realized in a 250 nm SiGe BiCMOS electronic-photonic integrated technology.

The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.

State-of-the-art SiGe BiCMOS technologies leverage the maturity of deep-submicron silicon CMOS processing with bandgap-engineered SiGe HBTs in a single platform that is suitable for a wide variety of high performance and highly-integrated applications (e.g., system-on-chip (SOC), system-in-package (SiP)). Due to their bandgap-engineered base, SiGe HBTs are also naturally suited for cryogenic electronics and have the potential to replace the costly de facto technologies of choice (e.g., Gallium-Arsenide (GaAs) and Indium-Phosphide (InP)) in many cryogenic applications such as radio astronomy. This work investigates the response of mixed-signal circuits (both RF and analog circuits) when operating in extreme environments, in particular, at cryogenic temperatures and in radiation-rich environments. The ultimate goal of this work is to attempt to fill the existing gap in knowledge on the cryogenic and radiation response (both single event transients (SETs) and total ionization dose (TID)) of specific RF and analog circuit blocks (i.e., RF switches and voltage references). The design approach for different RF switch topologies and voltage references circuits are presented. Standalone Field Effect Transistors (FET) and SiGe HBTs test structures were also characterized and the results are provided to aid in the analysis and understanding of the underlying mechanisms that impact the circuits' response. Radiation mitigation strategies to counterbalance the damaging effects are investigated. A comprehensive study on the impact of cryogenic temperatures on the RF linearity of SiGe HBTs fabricated in a new 4th-generation, 90 nm SiGe BiCMOS technology is also presented.

Der thermische Widerstand ist eine wichtige Kenngröße von Silicium-Germanium-Hetero-Bipolartransistoren (SiGe-HBTs). Bisher kam es bei der quantitativen Bestimmung der thermischen Widerstände von SiGe-HBTs zu deutlichen Abweichungen zwischen Simulation und Messung. Der Unterschied zwischen Simulation und Messung betrug bei den untersuchten HBTs mehr als 30 Prozent. Diese Arbeit widmet sich der Aufklärung und Beseitigung der möglichen Ursachen hierfür. Zu diesem Zweck werden als erstes die Messmethoden analysiert. Es zeigt sich, dass die bisher verwendete Extraktionsmethode sensitiv auf den Early-Effekt (Basisweitenmodulation) reagiert. Im Rahmen der Untersuchungen wurde ein neues Extraktionsverfahren entwickelt. Die neue Extraktions­methode ist unempfindlich gegenüber dem Early-Effekt. Mit Bauelemente­simulationen wird erstmalig die Wirkung des Seebeck-Effektes (Thermospannungen) auf die elektrisch extrahierten thermischen Widerstände demonstriert. Der Seebeck-Effekt bewirkt, dass die elektrisch extrahierten thermischen Widerstände der untersuchten HBTs nahezu 10 Prozent kleiner als die erwarteten Werte sind. Dieser Effekt wurde bisher nicht beachtet und wird hier erstmals nachgewiesen. Weiterhin wird die Abhängigkeit des thermischen Widerstandes vom Arbeitspunkt untersucht. Dabei hat sich gezeigt, dass bis zu einer Basis-Emitter-Spannung von 0,91 Volt die geometrische Form des Wärme abgebenden Gebietes unabhängig vom Arbeitspunkt ist. Anhand von Messungen wird gezeigt, dass die Dotierung die spezifische Wärmeleitfähigkeit von Silicium reduziert. Die Abnahme wird für Dotierungen größer als 1*1019 cm‑3 deutlich sichtbar. Ist die Dotierung größer als 1*1020 cm‑3, beträgt die Abnahme der spezifischen Wärmeleitfähigkeit mehr als 75 Prozent. Mithilfe einer Simulatorkalibrierung wird die spezifische Wärmeleitfähigkeit als Funktion der Dotierung bestimmt. Die erhaltene Funktion kann künftig beim thermischen Entwurf von HBTs verwendet werden. Somit können zukünftig genauere Vorhersagen zum thermischen Widerstand der HBTs gemacht werden. Dies ermöglicht zuverlässigere Aussagen darüber, wie Änderungen des Transistordesigns zur Minimierung des thermischen Widerstandes beitragen. / The thermal resistance is an important parameter of silicon-germanium heterojunction bipolar transistors (SiGe HBTs). Until now, the quantitative determination of the thermal resistance showed significant differences between measurements and simulations. The difference between simulation and measurement of the investigated HBTs was more than 30 percent. This thesis devotes the clarification and elimination of potential sources for it. For this purpose, the measurement methods are analyzed at first. It is shown, that the currently used extraction method is sensitive to the Early effect (basewidth modulation). A now extraction method was developed, which is not sensitive to the Early effect. For the first time, the influence of the Seebeck effect (thermoelectric voltages) on the electrically extracted thermal resistance is shown by device simulations. The Seebeck effect leads to a 10 percent lower extracted thermal resistances compared to the expected values of the investigated HBTs. This effect was not taken into account up to now and is demonstrated here for the first time. Furthermore, the dependence of the thermal resistance on the operating point was investigated. The results show that the shape of the heat source is independent of the operating point if the base emitter voltage is smaller than 0.91 volt. The thermal conductivity of silicon is decreased by increasing doping concentrations. This is shown by measurements. The reduction of the thermal conductivity is well observable for doping concentrations higher than 1*1019 cm‑3. For doping concentration higher than 1*1020 cm‑3 the reduction amounts to more than 75 percent. The thermal conductivity was determined as a function of the doping concentration with the aid of a simulator calibration. This function can be used in the future thermal design of HBTs. It facilitates the optimization of the HBTs with respect to a minimal thermal resistance.

Ce manuscrit présente l'intégration conjointe d'un banc de mesure de bruit de phase et de résonateurs BAW sur lesquels doit s'effectuer la mesure. Une tendance actuelle vise à intégrer à côté de systèmes plus ou moins complexes, des circuits permettant d'en faciliter les tests. L'intégration du banc de mesure de bruit de phase permet de nous affranchir des contraintes provenant de la mesure externe sous pointes et du coût élevé associé. L'intégration simultanée des circuits de tests avec les systèmes à mesurer, permet également d'exploiter pleinement les possibilités d'appariement de composants disponibles sur un même substrat. Ce type de mesure On-Chip simplifie considérablement la procédure de test, en minimisant l'utilisation de matériel de mesure externe encombrant et de coût élevé. Elle évite aussi les dispersions inhérentes à l'utilisation de composants discrets externes, offrant la possibilité de suivre facilement l'évolution des caractéristiques du système, soit dans le temps, soit après divers types de dégradations. Cette mesure intégrée conduit naturellement à la conception de circuits autotestables, et donc autoreconfigurables. Notre travail de thèse a consisté à définir l'architecture, ainsi que le dimensionnement des différents éléments du banc de mesure, en fonction de la précision de mesure souhaitée. Nous avons montrer qu'un système d'instrumentation performant peut s'intégrer dans une technologie SiGe standard.

Wireless operation, near-field or far-field, is a core functionality of any mobile or autonomous system. These systems are battery operated or most often utilize energy scavenging as a means of power generation. Limited access to power, expected long and uninterrupted operation, and constrained physical parameters (e.g. weight and size), which limit overall power harvesting capabilities, are factors that outline the importance for innovative low-power approaches and designs in advanced low-power wireless applications. Low-power approaches become especially important for the wireless transceiver, the block in charge of wireless/remote functionality of the system, as this block is usually the most power hungry component in an integrated system-on-chip (SoC). Three such advanced applications with stringent power requirements are examined including space-based exploratory remote sensing probes and their associated radiation effects, millimeter-wave phased-array radar for high-altitude tactical and geological imaging, and implantable biomedical devices (IMDs), leading to the proposal and implementation of low-power wireless solutions for these applications in SiGe BiCMOS and CMOS and platforms.

Le travail de recherche présenté dans ce mémoire s'inscrit dans l'objectif général d'étudier la faisabilité de filtres monolithiques radiofréquences (RF) à capacités commutées pour la radiocommunication mobile, et de pouvoir procéder à l'analyse et à la conception de ces filtres en technologie standard BiCMOS 0,35 μm. L'analyse comportementale de ces filtres a nécessité la mise au point d'un algorithme original basé sur le formalisme des matrices de conversion, dont le principe général consiste à effectuer une linéarisation des éléments non-linéaires autour du point de fonctionnement grand signal. Cette méthode d'analyse, spécialement utilisée pour l'analyse du bruit de phase des oscillateurs, semble à ce jour parmi les plus rigoureuses et les plus efficaces en terme de temps de calcul pour l'analyse de ce type de filtres. Traditionnellement, à basse fréquence la commande de ces filtres est réalisée à l'aide d'un registre à décalage. Cependant, cette technique n'est pas envisageable en RF. Une solution originale qui consiste à commander le filtre à partir d'un oscillateur en anneau contrôlé en tension et de portes logiques " ou exclusif " a été proposée. Grâce à cette solution, il a été montré que l'association d'un tel circuit de commande appliqué à ce type de filtre présente des avantages importants et par conséquent devrait le rendre beaucoup plus attractif pour les concepteurs. Pour répondre aux spécifications de la radiocommunication mobile, la structure classique du filtre a été optimisée pour réduire le facteur du bruit et augmenter la dynamique, ainsi une nouvelle architecture (filtre LC à capacités commutées) a été proposée. Des simulations ont été réalisées sur l'ensemble du circuit afin de prévoir les dégradations éventuelles qui peuvent être générées par ces circuits lors d'une transmission numérique (ex. p/4-DQPSK) et d'étudier ainsi l'impact du bruit de phase (gigue temporelle) généré par le circuit de commande sur le comportement du filtre. Parallèlement, un prototype composé d'un filtre LC à capacités commutées et de son circuit de commande a été fabriqué en technologie standard BiCMOS 0,35 mm, sur une puce de taille de 1,1 x 1,75 mm². Ce premier circuit a permis de prouver la faisabilité de cette architecture dans le domaine des RF. Les résultats expérimentaux confirment les simulations et sont susceptibles de rendre cette architecture originale attractive pour des applications radiofréquences.

"2009" / Thesis (MSc (Hons))--Macquarie University, Faculty of Science, Dept. of Physics and Engineering, 2010. / Bibliography: p. 163-166. / Introduction -- Design theory and process technology -- 15GHz oscillator implementations -- 24GHz oscillator implementation -- Frequency prescaler implementation -- MMIC fabrication and measurement -- Conclusion. / Advances in Silicon Germanium (SiGe) Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technology has caused a recent revolution in low-cost Monolithic Microwave Integrated Circuit (MMIC) design. -- This thesis presents the design, fabrication and measurement of four MMICs for frequency synthesis, manufactured in a commercially available IBM 0.18μm SiGe BiCMOS technology with ft = 60GHz. The high speed and low-cost features of SiGe Heterojunction Bipolar Transistors (HBTs) were exploited to successfully develop two single-ended injection-lockable 15GHz Voltage Controlled Oscillators (VCOs) for application in an active Ka-Band antenna beam-forming network, and a 24GHz differential cross-coupled VCO and 1/6 synchronous static frequency prescaler for emerging Ultra Wideband (UWB) automotive Short Range Radar (SRR) applications. -- On-wafer measurement techniques were used to precisely characterise the performance of each circuit and compare against expected simulation results and state-of-the-art performance reported in the literature. -- The original contributions of this thesis include the application of negative resistance theory to single-ended and differential SiGe VCO design at 15-24GHz, consideration of manufacturing process variation on 24GHz VCO and prescaler performance, implementation of a fully static multi-stage synchronous divider topology at 24GHz and the use of differential on-wafer measurement techniques. -- Finally, this thesis has llustrated the excellent practicability of SiGe BiCMOS technology in the engineering of high performance, low-cost MMICs for frequency synthesis in millimeterwave (mm-wave) devices. / Mode of access: World Wide Web. / xxii, 166 p. : ill (some col.)