Submitted by Kamila Costa (kamilavasconceloscosta@gmail.com) on 2015-06-15T22:12:07Z No. of bitstreams: 1 Dissertacao-Wheidima C de Melo.pdf: 2703087 bytes, checksum: e6e1c33a03cbfdb7ab483f0f6f9e6dc7 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2015-06-16T15:15:11Z (GMT) No. of bitstreams: 1 Dissertacao-Wheidima C de Melo.pdf: 2703087 bytes, checksum: e6e1c33a03cbfdb7ab483f0f6f9e6dc7 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2015-06-16T15:16:09Z (GMT) No. of bitstreams: 1 Dissertacao-Wheidima C de Melo.pdf: 2703087 bytes, checksum: e6e1c33a03cbfdb7ab483f0f6f9e6dc7 (MD5) / Made available in DSpace on 2015-06-16T15:16:09Z (GMT). No. of bitstreams: 1 Dissertacao-Wheidima C de Melo.pdf: 2703087 bytes, checksum: e6e1c33a03cbfdb7ab483f0f6f9e6dc7 (MD5) Previous issue date: 2014-06-27 / Não Informada / Traditionally, electromyographic signals are compressed to one-dimensional techniques, which are specifically developed for this purpose. However, some studies have shown that the compression of biological signals such as images, via its pre-processing and rearrangement on a two-dimensional array, can lead to good results. The present work an investigation of the compression electromyographic signals like images, three main contributions: the use of new encoders, the development of new pre-processing techniques and modification of the coding core of a specific compressor, so that existing redundancies are better exploited. With respect to the pre-processing of the signal, two new techniques are introduced: ordering a percentage difference and targeting similarity which have the potential to increase the performance of encoded pictures. Optionally for compression of electromyographic signals, propose to the high efficiency video coding encoder, which features state of the art in video compression. Furthermore, an investigation of the paradigm that uses recurrence multiscale standards, known as multidimensional multiscale parser, is also presented. In summary, the encoder adapts to working with the biological signal by replacing its prediction techniques to improve the exploitation of redundancy, the result of which is termed Bio-MMP. The experiments performed with real electromyographic signals show that the proposed techniques are effective, providing better results than the state of the art in the literature. / Tradicionalmente, sinais eletromiográficos são comprimidos com técnicas unidimensionais, que são desenvolvidas especificamente para esse fim. No entanto, alguns trabalhos têm demonstrado que a compressão de sinais biológicos como imagens, através do seu pré-processamento e rearranjo em uma matriz bidimensional, pode levar a bons resultados. O presente trabalho apresenta uma investigação sobre a compressão de sinais eletromiográficos como imagens, com três principais contribuições: a utilização de novos codificadores, o desenvolvimento de novas técnicas de pré-processamento e a modificação do núcleo de codificação de um compressor específico, de modo que as redundâncias existentes sejam melhor exploradas. No que diz respeito ao pré-processamento do sinal, duas novas técnicas são introduzidas: a ordenação por diferença percentual e a segmentação por similaridade, que apresentam o potencial de aumentar o desempenho do codificados de imagens. Como opção para compressão de sinais eletromiográficos, propõem-se o codificador high efficiency video coding, que apresenta o estado da arte em compressão de vídeo. Além disso, uma investigação do paradigma que utiliza recorrência de padrões multiescalas, conhecido como multidimensional multiscale parser, também é apresentada. Em resumo, adapta-se o codificador para trabalhar com o sinal biológico, através da substituição das suas técnicas de predição, de modo a melhorar a exploração de redundâncias, cujo resultado é denominado de MMP-Bio. Os experimentos realizado com sinais eletromiográficos reais mostram que as técnicas propostas são eficazes, proporcionando resultados superiores ao estado da arte presente na literatura.

Esta tese de doutorado apresenta o projeto de uma arquitetura de memória híbrida energeticamente eficiente baseada em memórias do tipo scratchpad (Hy-SVM) para a codificação paralela de vídeos segundo o padrão HEVC. A codificação de vídeo se destaca como uma parte extremamente complexa nas aplicações de processamento de vídeo. O padrão HEVC traz inovações que complicam fortemente os requerimentos de memória de tais aplicações, principalmente devido a: (a) novas estruturas de codificação, as quais agravam a complexidade computacional por proporcionarem muitas modos possíveis de codificação que devem ser analisados; além do (b) suporte de alto nível à paralelização da codificação por meio do particionamento das unidades de codificação em múltiplos Tiles, o qual provê a aceleração da performance dos codificadores, porém, ao mesmo tempo, adiciona grandes desafios à infraestrutura de memória. O principal gargalo em termos de comunicação com a memória externa e de armazenamento interno (dentro do chip do codificador) é dados pelas informações dos quadros de referência: que consiste em uma série de quadros completos já codificados (e reconstruídos) que devem ser mantidos em memória e acessados de forma intensa durante o processamento dos quadros futuros. Devido ao grande volume de dados que são necessários para representar os quadros de referência, estes são tipicamente armazenados na memória externa dos codificadores (principalmente quando vídeos de alta e ultra alta resolução são processados) A arquitetura proposta Hy-SVM está inserida em um sistema de codificação baseado no particionamento dos quadros do vídeo de entrada em múltiplos Tiles, de forma a habilitar a codificação paralela das informações segundo o padrão HEVC: neste cenário, cada Tile é assinalado para uma específica unidade de processamento do codificador HEVC, o qual executa o processamento dos diferentes Tiles em paralelo. A ideias chave da arquitetura Hy- SVM incluem: projeto e gerenciamento de memórias para a aplicação específica de codificação de vídeo; uso de múltiplos níveis de memórias privadas e compartilhadas, com o objetivo de explorar o reuso de dados intra-Tile e inter-Tiles de forma combinada; uso de memórias do tipo scratchpad (SPMs) para o armazenamento interno da informações de forma eficiente em termos de consumo de energia; projeto de memórias híbridas utilizando as tecnologias SRAM e STTRAM como base. Uma metodologia de projeto é proposta para a arquitetura Hy-SVM, a qual aproveita propriedades específicas da aplicação para, de forma adequada, definir os parâmetros de projeto das memórias híbridas. De forma a prover adaptação em tempo de execução (para ambas as memórias on-chip e off-chip), a arquitetura Hy-SVM integra uma camada de gerenciamento composta pelas seguintes estratégias (1) predição do overlap (sobreposição de acessos), o qual busca identificar o comportamento dos acessos redundantes entre diferentes unidades de processamento do codificador HEVC a partir da análise dos acessos à memória das codificações dos quadros passados do vídeo, com o objetivo de aumentar o potencial de exploração do reuso de dados inter-Tiles; (2) gerenciamento dos acessos à memória externa, responsável por balancear a vazão de dados com a memória acumulada entre as múltiplas unidades de processamento do codificador HEVC paralelo, com o objetivo de melhorar o uso do barramento de comunicação com a memória externa; e (3) gerenciamento de dados das SPMs implementadas a partir de células de memória STT-RAM, o qual alivia estas células de acessos de escrita com alta atividade de chaveamento dos bits armazenados, com o objetivo de aumentar o tempo de vide destas células, bem como reduzir as penalidades relativas à ineficiência dos acessos de escrita nas memórias STT-RAM. O conhecimento específico da aplicação foi utilizado nas estratégias de gerenciamento em tempo de execução das seguintes formas: explorando parâmetros da codificação HEVC e realizando monitorando em tempo real dos acessos à memória realizados pelo codificador Estas informações são utilizadas tanto pelas técnicas de gerenciamento, quanto pelas metodologias de projeto das memórias. Baseadas nas decisões tomadas pela camada de gerenciamento, a arquitetura Hy-SVM integra unidades de gerenciamento de acessos à memória (memory access management units – MAMUs) para controlar as dinâmicas de acesso das memórias SPM privadas e compartilhadas. Além disso, unidades adaptativas de gerenciamento de potência (adaptive power management units – APMUs) são capazes de reduzir o consumo de energia interno do chip do codificador a partir das estimativas precisas de formação dos overlaps. Os resultados obtidos por meio dos experimentos realizados demonstram economias de consumo energético da arquitetura Hy-SVM, quando comparada a trabalhos relacionados, sob diversos cenários de teste. Quando comparada a estratégias de reuso de dados tradicionais para codificadores de vídeo, como o esquema Level-C, a exploração do reuso de dados combinado nos níveis intra-Tile e inter-Tiles provê 69%-79% de redução de energia. Considerando as arquiteturas de memória de vídeo com foco no padrão HEVC, os ganhos variaram desde 2,8% (pior caso) até 67% (melhor caso) Da perspectiva do consumo de energia relacionado à comunicação com a memória externa, a arquitetura Hy-SVM é capaz de melhorar o reuso de dados (por explorar também o reuso de dados inter-Tiles), resultando em um consumo de energia on-chip 11%-17% menor. Além disso, as APMUs contribuem para reduzir o consumo de energia on-chip da arquitetura Hy-SVM em 56%-95%, para os cenários de teste analisados. Desta forma, comparada aos trabalhos relacionados, a arquitetura Hy-SVM apresenta o menor consumo energético on-chip. O gerenciamento da vazão da comunicação com a memória externa é capaz de reduzir as variações de largura de banda em 37%-83%, quando comparado à ordem tradicional de processamento, para cenários de teste com 4 e 16 Tiles sendo processados em paralelo pelo codificador HEVC. O gerenciamento de dados pôde, de forma significativa, estender o tempo de vida das células de memória STT-RAM, alcançando 0,83 de tempo de vida normalizado (métrica adotada para comparação, ficando muito próximo do caso ideal). Além disso, as sobrecargas causadas pela implementação das unidades de gerenciamento não afetam de foram significativa a performance e a eficiência energética da arquitetura Hy- SVM propostas por este trabalho. / This Thesis presents the design of an energy-efficient hybrid scratchpad video memory architecture (called Hy-SVM) for parallel High-Efficiency Video Coding. Video coding stands out as a high complex part in the video processing applications. HEVC standard brought innovations that increase the memory requirements, mainly due to: (a) the novel coding structures, which aggravates the computational complexity by providing a wider range of possibilities to be analyzed; and (b) the high-level parallelism features provided by the Tiles partitioning, which provides performance acceleration, but, at the same time, strongly adds hard challenges to the memory infrastructure. The main bottleneck in terms of external memory transmission and on-chip storage is the reference frames data: which consists of already coded (and reconstructed) entire frames that must be stored and intensively accessed during the encoding process of future frames. Due to the large volume of data required to represent the reference frames, they are typically stored in the external memory (especially when highdefinition videos are targeted). The proposed Hy-SVM architecture is inserted in a video coding system, which is based on multiple Tiles partitioning to enable parallel HEVC encoding: each Tile is assigned to a specific processing unit. The key ideas of Hy-SVM include: applicationspecific design and management; combined multiple levels of private and shared memories that jointly exploit intra-Tile and inter-Tiles data reuse; scratchpad memories (SPMs) as energyefficient on-chip data storage; combined SRAM and STT-RAM hybrid memory (HyM) design We propose a design methodology for Hy-SVM that leverages application-specific properties to properly define the HyMs parameters. In order to provide run-time adaptation (for both offand on-chip parts), Hy-SVM integrates a memory management layer composed of: (1) overlap prediction, which has the goal of identifying the redundant memory access behavior by analyzing monitored past frames encoding to increase inter-Tiles data reuse exploitation; (2) memory pressure management, which aims on balancing the Tiles-accumulated memory pressure targeting on improving external memory communication channel usage; and (3) lifetime-aware data management scheme that alleviates STT-RAM SPMs of high bit-toggling write accesses to increase the their cells lifetime, as well as to reduce overhead issues related to poor write characteristics of STT-RAM. Application-specific knowledge was exploited by inheriting HEVC properties and performing run-time monitoring of memory accesses. Such information is used to properly design the on-chip video memories, as well as being utilized as input parameters of the run-time memory management layer. Based on the run-time decisions from the proposed Hy-SVM management strategies, Hy-SVM integrates distributed memory access management units (MAMUs) to control the access dynamics of private and shared SPMs. Additionally, adaptive power management units (APMUs) are able to strongly reduce on-chip energy consumption due to an accurate overlap prediction The experimental results demonstrate Hy-SVM overall energy savings over related works under various HEVC encoding scenarios. Compared to traditional data reuse schemes, like Level-C, the combined intra-Tile and inter-Tiles data reuse provides 69%-79% of energy reduction. Regarding related HEVC video memory architectures, the savings varied from 2.8% (worst case) to 67% (best case). From the external memory perspective, Hy-SVM can improve data reuse (by also exploiting inter-Tiles data redundancy), resulting on 11%-71%% of reduced off-chip energy consumption. Additionally, our APMUs contribute by reducing on-chip energy consumption of Hy-SVM by 56%-95%, for the evaluated HEVC scenarios. Thus, compared to related works, Hy-SVM presents the lowest on-chip energy consumption. The memory pressure management scheme can reduce the variations in the memory bandwidth by 37%-83% when compared to the traditional raster scan processing for 4- and 16-core parallelized HEVC encoder. The lifetime-aware data management significantly extends the STT-RAM lifetime, achieving 0.83 of normalized lifetime (near to the optimal case). Moreover, the overhead of implementing our management units insignificantly affects the performance and energyefficiency of Hy-SVM.

Dry powder inhalers (DPIs) are advantageous for delivering medication to the lungs for the treatment of respiratory diseases because of the stability of the powders, relative low cost, synchronization of inhalation and dose delivery, and many design options that can be used for optimization. However, currently marketed DPIs are very inefficient in delivering medications to the lungs. This study has developed multiple new high efficiency DPIs for use with spray dried excipient enhanced growth (EEG) powder formulations based on the following platforms: capsule-based for oral inhalation, high-dose for oral inhalation, inline with 3D rod array dispersion, and inline with capillary jet dispersion. The capsule-based DPIs for oral inhalation implemented a 3D rod array for aerosol dispersion with optimal designs producing mass median aerodynamic diameters (MMADs) in the range of 1.3-1.5 µm and emitted doses in the range of 79-81%. Keys to inhaler success were the orientation of the capsule and inclusion of the 3D rod array. For the high-dose oral inhaler, performance was similar to the optimized capsule-based devices, while aerosolizing a much larger mass of powder. Surprisingly, removal of the fluidized bed of spheres improved performance producing a simple high dose device containing only a single dose sphere. The inline device using the 3D rod array was effective in producing particles of approximately 1.5 µm, at flow rates consistent with high flow therapy using a 1 L ventilation bag as the delivery mechanism. Using a capillary jet as the dispersion mechanism, further advances were made to allow for both delivery using a low volume (LV) of air and delivery in low flow therapy. This easily adaptable platform was able to produce a high quality aerosol out of a nasal cannula with an ED greater than 60% and a size (~2 µm) that should produce minimal extrathoracic losses. In conclusion, this study demonstrates (i) the design and optimization of DPIs capable of delivering EEG aerosols to the lungs using oral inhalation, (ii) the ability to deliver EEG aerosols using N2L aerosol administration, and (iii) the design of a new flexible LV-DPI device that is easily adaptable to multiple patients and delivery platforms, which are greatly needed in clinical environments.

<p>The purpose of this master thesis was to study if the drain efficiency of power amplifiers can be maintained at power back off using a technique called load modulation.</p><p>The amplifier classes studied are E, F and D-1. The target figure was to obtain a 10 to 12 dB dynamic range of amplitude with reasonable efficiency. Studies of power amplifiers have been made to understand how power is generated. Several different load modulation networks have been evaluated. Attempts to derive design equations for the modulation networks have also been done.</p><p>The thesis work was carried out with simulations in ADS 2006. As active devices commercially available bare-die transistor models have been used. The power rating of the dies are 15 W.</p><p>A dynamic range of amplitude of over 15 dB has been achieved with drain efficiency greater than 60 percent. The peak output power is in the 40 – 45 dBm range.</p>

The objective of this thesis is to develop low-cost high-efficiency crystalline silicon solar cells which are at the right intersection of cost and performance to make photovoltaics (PV) affordable. The goal was addressed by improving the optical and electrical performance of silicon solar cells through process optimization, device modeling, clever cell design, fundamental understanding, and minimization of loss mechanisms. To define the right intersection of cost and performance, analytical models to assess the premium or value associated with efficiency, temperature coefficient, balance of system cost, and solar insolation were developed and detailed cost analysis was performed to quantify the impact of key system and financial parameters in the levelized cost of electricity from PV.

For many years batteries have been used as the main power sources for portable electronic devices. However, the rate of scaling in integrated circuits and micro-electro-mechanical systems (MEMS) has been much higher than that of the batteries technology. Therefore, a need to replace these temporary energy reservoirs with small sized continuously charged energy supply units has emerged. These units, named as energy harvesters, use several types of ambient energy sources such as heat, light, and vibration to provide energy to intelligent systems such as sensor nodes. Among the available types, vibration based electromagnetic (EM) energy harvesters are particularly interesting because of their simple structure and suitability for operation at low frequency values (&lt / 10 Hz), where most vibrations exits. However, since the generated EM power and voltage is relatively low at low frequencies, high performance interface electronics is required for efficiently transferring the generated power from the harvester to the load to be supplied. The aim of this study is to design low power and efficient interface electronics to convert the low voltage and low power generated signals of the EM energy harvesters to DC to be usable by a real application. The most critical part of such interface electronics is the AC/DC converter, since all the other blocks such as DC/DC converters, power managements units, etc. rely on the rectified voltage generated by this block. Due to this, several state-of-the-art rectifier structures suitable for energy harvesting applications have been studied. Most of the previously proposed rectifiers have low conversion efficiency due to the high voltage drop across the utilized diodes. In this study, two rectifier structures are proposed: one is a new passive rectifier using the Boot Strapping technique for reducing the diode turn-on voltage values / the other structure is a comparator-based ultra low power active rectifier. The proposed structures and some of the previously reported designs have been implemented in X-FAB 0.35 &micro / m standard CMOS process. The autonomous energy harvesting systems are then realized by integrating the developed ASICs and the previously proposed EM energy harvester modules developed in our research group, and these systems have been characterized under different electromechanical excitation conditions. In this thesis, five different systems utilizing different circuits and energy harvesting modules have been presented. Among these, the system utilizing the novel Boot Strap Rectifier is implemented within a volume of 21 cm3, and delivers 1.6 V, 80 &micro / A (128 &micro / W) DC power to a load at a vibration frequency of only 2 Hz and 72 mg peak acceleration. The maximum overall power density of the system operating at 2 Hz is 6.1 &micro / W/cm3, which is the highest reported value in the literature at this operation frequency. Also, the operation of a commercially available temperature sensor using the provided power of the energy harvester has been shown. Another system utilizing the comparator-based active rectifier implemented with a volume of 16 cm3, has a dual rail output and is able to drive a 1.46 V, 37 &micro / A load with a maximum power density of 6.03 &micro / W/cm3, operating at 8 Hz. Furthermore, a signal conditioning system for EM energy harvesting has also been designed and simulated in TSMC 90 nm CMOS process. The proposed ASIC includes a highly efficient AC-DC converter as well as a power processing unit which steps up and regulates the converted DC voltages using an on-chip DC/DC converter and a sub-threshold voltage regulator with an ultra low power management unit. The total power consumption on the totally passive IC is less than 5 &micro / W, which makes it suitable for next generation MEMS-based EM energy harvesters. In the frame of this study, high efficiency CMOS rectifier ICs have been designed and tested together with several vibration based EM energy harvester modules. The results show that the best efficiency and power density values have been achieved with the proposed energy harvesting systems, within the low frequency range, to the best of our knowledge. It is also shown that further improvement of the results is possible with the utilization of a more advanced CMOS technology.

The purpose of this master thesis was to study if the drain efficiency of power amplifiers can be maintained at power back off using a technique called load modulation. The amplifier classes studied are E, F and D-1. The target figure was to obtain a 10 to 12 dB dynamic range of amplitude with reasonable efficiency. Studies of power amplifiers have been made to understand how power is generated. Several different load modulation networks have been evaluated. Attempts to derive design equations for the modulation networks have also been done. The thesis work was carried out with simulations in ADS 2006. As active devices commercially available bare-die transistor models have been used. The power rating of the dies are 15 W. A dynamic range of amplitude of over 15 dB has been achieved with drain efficiency greater than 60 percent. The peak output power is in the 40 – 45 dBm range.

This work focusses on the high brightness performance of phosphorescent organic light-emitting diodes (OLEDs). The use of phosphorescent emitter molecules in OLEDs is essential to realize internal electron-photon conversion efficiencies of 100 %. However, due to their molecular nature, the excited triplet states have orders of magnitude longer time constants compared to their fluorescent counterparts which, in turn, strongly increases the probability of bimolecular annihilation. As a consequence, the efficiencies of phosphorescent OLEDs decline at high brightness – an effect known as efficiency roll-off, for which it has been shown to be dominated by triplet-triplet annihilation (TTA). In this work, TTA of the archetype phosphorescent emitter Ir(ppy)3 is investi- gated in time-resolved photoluminescence experiments. For the widely used mixed system CBP:Ir(ppy)3, host-guest TTA – an additional unwanted TTA channel – is experimentally observed at high excitation levels. By using matrix materials with higher triplet energies, this effect is efficiently suppressed, however further studies show that the efficiency roll-off of Ir(ppy)3 is much more pronounced than predicted by a model based on Förster-type energy transfer, which marks the intrinsic limit for TTA. These results suggest that the emitter molecules show a strong tendency to form aggregates in the mixed film as the origin for enhanced TTA. Transmission electron microscopy images of Ir(ppy)3 doped mixed films give direct proof of emitter aggregates. Based on these results, two concepts are developed that improve the high brightness performance of OLEDs. In a first approach, thin intrinsic matrix interlayers are incorporated in the emission layer leading to a one-dimensional exciton confinement that suppresses exciton migration and, consequently, TTA. The second concept reduces the efficiency roll-off by using an emitter molecule with slightly differ- ent chemical structure, i.e. Ir(ppy)2(acac). Compared to Ir(ppy)3, this emitter has a much smaller ground state dipole moment, suggesting that the improved performance is a result of weaker aggregation in the mixed film. The knowledge gained in the investigation of triplet-triplet annihilation is further used to develop a novel emission layer design for white organic LEDs. It comprises three phosphorescent emitters for blue, green, and red emission embedded in a multilayer architecture. The key feature of this concept is the matrix material used for the blue emitter FIrpic: Its triplet energy is in resonance with the FIrpic excited state energy which enables low operating voltages and high power efficiencies by reducing thermal relaxation. In order to further increase the device efficiency, the OLED architecture is optically optimized using high refractive index substrates and thick electron transport layers. These devices reach efficiencies which are on par with fluorescent tubes – the current efficiency benchmark for light sources. / Diese Arbeit richtet ihren Fokus auf die Untersuchung der Leistungsfähigkeit von phosphoreszenten, Licht-emittierenden organischen Dioden (OLEDs) im Bereich hoher Betriebshelligkeiten. Phosphoreszente Emittermoleku ̈le werden in OLEDs eingesetzt, um interne Elektron-Photon Konversionseffizienzen von 100% zu erreichen. Begründet in ihrer chemischen Struktur, weisen die angeregten Triplett-Zustände dieser Emitter um Größenordnungen längere Zeitkonstanten als die Emission fluo- reszenter Materialien auf, sodass die Wahrscheinlichkeit bimolekularer Auslöschung stark ansteigt. Dies resultiert in einem deutlichen Effizienzrückgang phosphoreszenter OLEDs bei großen Leuchtdichten. Dieser als Roll-off bekannter Effekt wird bei hohen Anregungsdichten hauptsächlich durch Triplett-Triplett Annihilation (TTA) bestimmt. In der Arbeit wird TTA an einem Modellmolekül, dem phosphoreszenten Emit- ter Ir(ppy)3, in zeitaufgelösten Photolumineszenz Experimenten untersucht. Für das bekannte Emittersystem CBP:Ir(ppy)3 wird bei hohen Anregungsdichten Host-Guest TTA beobachtet, was einen zusätzlichen, ungewünschten TTA Kanal darstellt. Dieser Effekt wird durch das Verwenden von Matrix Materialien mit höherer Triplett Energie vermieden, jedoch zeigt sich in weiteren Untersuchungen, dass der Roll-off deutlich stärker ist als von einem auf Förster Energieübertrag basierendem Modell vorhergesagt, welches selbst ein intrinsisches Limit für TTA in phosphoreszenten Systemen beschreibt. Die Diskrepanz zwischen experimenteller Beobachtung und Modellvorhersage wird durch eine starke Tendenz des Emitters, Aggregate zu bilden, erklärt, was TTA deutlich verstärkt. Diese Aggregate werden mit Hilfe von Transmissionselektronenmikroskopie an Ir(ppy)3-dotierten Mischsystemen direkt nachgewiesen. Basierend auf diesen Resultaten werden zwei Konzepte entwickelt, um die Effizienz phosphoreszenter Systeme bei hohen Helligkeiten zu verbessern. Im ersten Ansatz werden dünne intrinsische Schichten des Matrixmaterials in die Emissionsschicht eingebaut, was die Exzitonenbewegung in einer Raumrichtung und damit auch TTA stark unterdrückt. Das zweite Konzept reduziert den Effizienz Roll-off durch die Verwendung eines phosphoreszenten Emitters Ir(ppy)2(acac) mit einer leicht abgeänderten Molekularstruktur. Im Vergleich mit Ir(ppy)3 weist dieser ein deutlich kleineres Dipolmoment im molekularen Grundzustand auf, wodurch die Aggregation vermindert wird. Aufbauend auf den Ergebnissen der TTA wird ein neuartiges Emissionsschicht-Design für weißes Licht entwickelt. In diesem Konzept werden drei phosphoreszente Materialien für blaue, grüne und rote Farbe in eine Vielschicht-Architektur eingebracht. Das Hauptmerkmal der Emissionsschicht ist die Wahl des Matrix-Materials für dem blauen Emitter FIrpic: Seine Triplett Energie liegt resonant zu dem FIrpic Triplett Zustand, wodurch niedrige Betriebsspannungen und hohe Leistungseffizienzen ermöglicht werden, da die thermische Relaxierung reduziert wird. Um die Ef- fizienz dieser weißen OLEDs weiter zu erhöhen, wird die entwickelte OLED Architektur zusätzlich durch die Verwendung von hochbrechenden Substraten und dicken Elektronen-Transportschichten optisch optimiert. Bei beleuchtungsrelevanten Helligkeiten erreichen diese OLEDs das Effizienzniveau von Leuchtstoffröhren – letztere stellen heute den Effizienz-Maßstab dar.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Throughout the twentieth century, the supply of electricity, mainly obtained from fossil fuels like oil and coal, it has supported the growth and transformation of the world economy. In the early years of this century, the scenario has changed to a new reality, the need for sustainable development. In other words, the challenge is to gradually replace the traditional sources of electricity from renewable energy sources, in which the solar photovoltaic energy has highlighted. Photovoltaic inverters may be constituted in different ways, presenting in recent decades a high research progress. The main study efforts focus on getting high efficiency, high power density and high reliability, to increase the overall performance of the photovoltaic installation. In this direction, this Master Thesis aims to propose, analyze, design and implement a single-phase grid-tied photovoltaic inverter, which provides high efficiency and high power density. This circuit is called Transformerless Photovoltaic Interleaved Multilevel NPC Inverter , that use uncoupled inductors, Gallium Nitride power transistors and employs interleaving strategy beside the LCL filter, synthesizing 9 levels. Are introduced studies on the operation, modulation and design methodology of power stages, considering the static performance. Results are presented for the 1 kW, in order to support the validity of the proposed topology in conjunction with the standard aspects, especially in relation to THD (Total Harmonic Distortion) of grid current, leakage current, efficiency and power density. / Durante todo o século XX, a oferta de energia elétrica, obtida principalmente a partir dos combustíveis fósseis como petróleo e o carvão mineral, deu suporte ao crescimento e as transformações da economia mundial. Já nos primeiros anos do século atual, o cenário mudou para uma nova realidade, a necessidade do desenvolvimento sustentável. Em outras palavras, o desafio é substituir gradativamente as fontes tradicionais de energia elétrica por fontes de energia renovável, onde a energia solar fotovoltaica tem destaque. Os conversores eletrônicos para sistemas fotovoltaicos, também chamados de inversores, podem ser constituídos de diversas maneiras, apresentando nas últimas décadas um acentuado progresso de pesquisa. Os principais esforços de estudo tem se concentrado em obter alto rendimento, alta densidade de potência e alta confiabilidade, de modo a aumentar o desempenho global da instalação fotovoltaica. Neste horizonte, esta dissertação tem por objetivo propor, analisar, projetar e implementar um inversor fotovoltaico monofásico, para aplicação conectada à rede, de alto rendimento e alta densidade de potência. Esta estrutura é denominada de Inversor Fotovoltaico NPC Multinível Intercalado sem Transformador , que utiliza indutores não acoplados, interruptores de Nitreto de Gálio e emprega a técnica interleaving junto ao filtro LCL, sintetizando 9 níveis. No decorrer do trabalho são introduzidos estudos relativos à operação, modulação, metodologia de projeto e estágios de potência, estabelecendo critérios, enquanto considera a performance estática. São apresentados resultados, observando a potência de 1 kW, com a finalidade de corroborar a validade da topologia proposta juntamente as normativas e aspectos que norteiam a aplicação, especialmente com respeito à THD (Total Harmonic Distortion) da corrente da rede, corrente de fuga, rendimento e densidade de potência.

Esta tese de doutorado apresenta o projeto de uma arquitetura de memória híbrida energeticamente eficiente baseada em memórias do tipo scratchpad (Hy-SVM) para a codificação paralela de vídeos segundo o padrão HEVC. A codificação de vídeo se destaca como uma parte extremamente complexa nas aplicações de processamento de vídeo. O padrão HEVC traz inovações que complicam fortemente os requerimentos de memória de tais aplicações, principalmente devido a: (a) novas estruturas de codificação, as quais agravam a complexidade computacional por proporcionarem muitas modos possíveis de codificação que devem ser analisados; além do (b) suporte de alto nível à paralelização da codificação por meio do particionamento das unidades de codificação em múltiplos Tiles, o qual provê a aceleração da performance dos codificadores, porém, ao mesmo tempo, adiciona grandes desafios à infraestrutura de memória. O principal gargalo em termos de comunicação com a memória externa e de armazenamento interno (dentro do chip do codificador) é dados pelas informações dos quadros de referência: que consiste em uma série de quadros completos já codificados (e reconstruídos) que devem ser mantidos em memória e acessados de forma intensa durante o processamento dos quadros futuros. Devido ao grande volume de dados que são necessários para representar os quadros de referência, estes são tipicamente armazenados na memória externa dos codificadores (principalmente quando vídeos de alta e ultra alta resolução são processados) A arquitetura proposta Hy-SVM está inserida em um sistema de codificação baseado no particionamento dos quadros do vídeo de entrada em múltiplos Tiles, de forma a habilitar a codificação paralela das informações segundo o padrão HEVC: neste cenário, cada Tile é assinalado para uma específica unidade de processamento do codificador HEVC, o qual executa o processamento dos diferentes Tiles em paralelo. A ideias chave da arquitetura Hy- SVM incluem: projeto e gerenciamento de memórias para a aplicação específica de codificação de vídeo; uso de múltiplos níveis de memórias privadas e compartilhadas, com o objetivo de explorar o reuso de dados intra-Tile e inter-Tiles de forma combinada; uso de memórias do tipo scratchpad (SPMs) para o armazenamento interno da informações de forma eficiente em termos de consumo de energia; projeto de memórias híbridas utilizando as tecnologias SRAM e STTRAM como base. Uma metodologia de projeto é proposta para a arquitetura Hy-SVM, a qual aproveita propriedades específicas da aplicação para, de forma adequada, definir os parâmetros de projeto das memórias híbridas. De forma a prover adaptação em tempo de execução (para ambas as memórias on-chip e off-chip), a arquitetura Hy-SVM integra uma camada de gerenciamento composta pelas seguintes estratégias (1) predição do overlap (sobreposição de acessos), o qual busca identificar o comportamento dos acessos redundantes entre diferentes unidades de processamento do codificador HEVC a partir da análise dos acessos à memória das codificações dos quadros passados do vídeo, com o objetivo de aumentar o potencial de exploração do reuso de dados inter-Tiles; (2) gerenciamento dos acessos à memória externa, responsável por balancear a vazão de dados com a memória acumulada entre as múltiplas unidades de processamento do codificador HEVC paralelo, com o objetivo de melhorar o uso do barramento de comunicação com a memória externa; e (3) gerenciamento de dados das SPMs implementadas a partir de células de memória STT-RAM, o qual alivia estas células de acessos de escrita com alta atividade de chaveamento dos bits armazenados, com o objetivo de aumentar o tempo de vide destas células, bem como reduzir as penalidades relativas à ineficiência dos acessos de escrita nas memórias STT-RAM. O conhecimento específico da aplicação foi utilizado nas estratégias de gerenciamento em tempo de execução das seguintes formas: explorando parâmetros da codificação HEVC e realizando monitorando em tempo real dos acessos à memória realizados pelo codificador Estas informações são utilizadas tanto pelas técnicas de gerenciamento, quanto pelas metodologias de projeto das memórias. Baseadas nas decisões tomadas pela camada de gerenciamento, a arquitetura Hy-SVM integra unidades de gerenciamento de acessos à memória (memory access management units – MAMUs) para controlar as dinâmicas de acesso das memórias SPM privadas e compartilhadas. Além disso, unidades adaptativas de gerenciamento de potência (adaptive power management units – APMUs) são capazes de reduzir o consumo de energia interno do chip do codificador a partir das estimativas precisas de formação dos overlaps. Os resultados obtidos por meio dos experimentos realizados demonstram economias de consumo energético da arquitetura Hy-SVM, quando comparada a trabalhos relacionados, sob diversos cenários de teste. Quando comparada a estratégias de reuso de dados tradicionais para codificadores de vídeo, como o esquema Level-C, a exploração do reuso de dados combinado nos níveis intra-Tile e inter-Tiles provê 69%-79% de redução de energia. Considerando as arquiteturas de memória de vídeo com foco no padrão HEVC, os ganhos variaram desde 2,8% (pior caso) até 67% (melhor caso) Da perspectiva do consumo de energia relacionado à comunicação com a memória externa, a arquitetura Hy-SVM é capaz de melhorar o reuso de dados (por explorar também o reuso de dados inter-Tiles), resultando em um consumo de energia on-chip 11%-17% menor. Além disso, as APMUs contribuem para reduzir o consumo de energia on-chip da arquitetura Hy-SVM em 56%-95%, para os cenários de teste analisados. Desta forma, comparada aos trabalhos relacionados, a arquitetura Hy-SVM apresenta o menor consumo energético on-chip. O gerenciamento da vazão da comunicação com a memória externa é capaz de reduzir as variações de largura de banda em 37%-83%, quando comparado à ordem tradicional de processamento, para cenários de teste com 4 e 16 Tiles sendo processados em paralelo pelo codificador HEVC. O gerenciamento de dados pôde, de forma significativa, estender o tempo de vida das células de memória STT-RAM, alcançando 0,83 de tempo de vida normalizado (métrica adotada para comparação, ficando muito próximo do caso ideal). Além disso, as sobrecargas causadas pela implementação das unidades de gerenciamento não afetam de foram significativa a performance e a eficiência energética da arquitetura Hy- SVM propostas por este trabalho. / This Thesis presents the design of an energy-efficient hybrid scratchpad video memory architecture (called Hy-SVM) for parallel High-Efficiency Video Coding. Video coding stands out as a high complex part in the video processing applications. HEVC standard brought innovations that increase the memory requirements, mainly due to: (a) the novel coding structures, which aggravates the computational complexity by providing a wider range of possibilities to be analyzed; and (b) the high-level parallelism features provided by the Tiles partitioning, which provides performance acceleration, but, at the same time, strongly adds hard challenges to the memory infrastructure. The main bottleneck in terms of external memory transmission and on-chip storage is the reference frames data: which consists of already coded (and reconstructed) entire frames that must be stored and intensively accessed during the encoding process of future frames. Due to the large volume of data required to represent the reference frames, they are typically stored in the external memory (especially when highdefinition videos are targeted). The proposed Hy-SVM architecture is inserted in a video coding system, which is based on multiple Tiles partitioning to enable parallel HEVC encoding: each Tile is assigned to a specific processing unit. The key ideas of Hy-SVM include: applicationspecific design and management; combined multiple levels of private and shared memories that jointly exploit intra-Tile and inter-Tiles data reuse; scratchpad memories (SPMs) as energyefficient on-chip data storage; combined SRAM and STT-RAM hybrid memory (HyM) design We propose a design methodology for Hy-SVM that leverages application-specific properties to properly define the HyMs parameters. In order to provide run-time adaptation (for both offand on-chip parts), Hy-SVM integrates a memory management layer composed of: (1) overlap prediction, which has the goal of identifying the redundant memory access behavior by analyzing monitored past frames encoding to increase inter-Tiles data reuse exploitation; (2) memory pressure management, which aims on balancing the Tiles-accumulated memory pressure targeting on improving external memory communication channel usage; and (3) lifetime-aware data management scheme that alleviates STT-RAM SPMs of high bit-toggling write accesses to increase the their cells lifetime, as well as to reduce overhead issues related to poor write characteristics of STT-RAM. Application-specific knowledge was exploited by inheriting HEVC properties and performing run-time monitoring of memory accesses. Such information is used to properly design the on-chip video memories, as well as being utilized as input parameters of the run-time memory management layer. Based on the run-time decisions from the proposed Hy-SVM management strategies, Hy-SVM integrates distributed memory access management units (MAMUs) to control the access dynamics of private and shared SPMs. Additionally, adaptive power management units (APMUs) are able to strongly reduce on-chip energy consumption due to an accurate overlap prediction The experimental results demonstrate Hy-SVM overall energy savings over related works under various HEVC encoding scenarios. Compared to traditional data reuse schemes, like Level-C, the combined intra-Tile and inter-Tiles data reuse provides 69%-79% of energy reduction. Regarding related HEVC video memory architectures, the savings varied from 2.8% (worst case) to 67% (best case). From the external memory perspective, Hy-SVM can improve data reuse (by also exploiting inter-Tiles data redundancy), resulting on 11%-71%% of reduced off-chip energy consumption. Additionally, our APMUs contribute by reducing on-chip energy consumption of Hy-SVM by 56%-95%, for the evaluated HEVC scenarios. Thus, compared to related works, Hy-SVM presents the lowest on-chip energy consumption. The memory pressure management scheme can reduce the variations in the memory bandwidth by 37%-83% when compared to the traditional raster scan processing for 4- and 16-core parallelized HEVC encoder. The lifetime-aware data management significantly extends the STT-RAM lifetime, achieving 0.83 of normalized lifetime (near to the optimal case). Moreover, the overhead of implementing our management units insignificantly affects the performance and energyefficiency of Hy-SVM.