MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.

Multilevel inverters are very popular for medium and high-voltage induction motor (IM) drive applications. They have superior performance compared to 2-level inverters such as reduced harmonic content in output voltage and current, lower common mode voltage and dv/dt, and lesser voltage stress on power switches. To get nearly sinusoidal current waveforms, the switching frequency of the conventional inverters have to be in¬creased. This will lead to higher switching losses and electromagnetic interference. The problem in using lower switching frequency is the introduction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching. Dodecagonal voltage space-vector based multilevel inverters have been proposed as an improvement over the conventional hexagonal space vector based inverters. They achieve complete elimination of 5th and 7th order harmonics throughout the modulation range. The linear modulation range is also extended by about 6.6%, since the dodecagon is closer to circle than a hexagon. The previous works on dodecagonal voltage space vector based VSI fed drives used voltage controlled PWM (VC-PWM). Although these controllers are more popular, they have inferior dynamic performance when compared to current controlled PWM (CC¬PWM). VSIs using current controlled PWM have excellent dynamic response, inherent short-circuit protection and are simple to implement. The conventional CC-PWM tech¬niques have large switching frequency variation and large current ripple in steady-state. xix As a result, there has been significant research interest to achieve current controlled VSI fed IM drives with constant switching frequency. Two current error space vector (CESV) based hysteresis controllers for dodecagonal voltage space-vector based VSI fed induction motor drives are proposed in this work. The proposed controllers achieve nearly constant switching frequency at steady state operation, similar to VC-SVPWM based VSI fed IM drives. They also have fast dynamic response while at the same time achieving complete elimination of fifth and seventh order harmonics for the entire modulation range, due to dodecagonal voltage vector switching. The first work proposes a nearly constant switching frequency current error space vector (CESV) based hysteresis controller for an IM drive with single dodecagonal voltage space vectors. Parabolic boundaries computed offline are used in the proposed controller. An open-end winding induction motor is fed from two inverters with asymmetrical DC link voltages, to generate the dodecagonal voltage space vectors. The drive scheme is first studied at different frequencies with a space vector based PWM (SVPWM) control, to obtain the current error space vector boundaries. The CESV boundary at each frequency can be approximated with four parabolas. These parabolic boundaries are used in the proposed controller to limit the CESV trajectory. Due to symmetries in the parabolas only two set of parabola parameters, at different frequencies, need to be stored. A generalized next vector selection logic, valid for all sectors and rotation direction, is used in the proposed controller. For this an axis transformation is done in all sectors, to bring the CESV trajectory to the first sector. The sector information is obtained from the estimated fundamental stator phase voltage. The proposed controller is extensively studied using vector control at different frequencies and transient conditions. This controller maintains nearly constant switching frequency at steady state operation, similar to VC-SVPWM inverters, while at the same time achieving better dynamic performance and complete elimination of 5th and 7th order harmonics throughout the modulation range. In the second work the nearly constant switching frequency current hysteresis con¬troller is extended to multilevel dodecagonal voltage space-vector based IM drives, with online computation of CESV boundaries. The multilevel dodecagonal space-vector dia¬gram has different types of triangles, and the previously proposed methods for multilevel hexagonal VSI based current hysteresis controllers cannot be used directly. The CESV trajectory of the VC-SVPWM, obtained for present triangular region, is used as the reference trajectory of the proposed controller. The CESV reference boundaries are com¬puted online, using switching dwell time and voltage error vector of each applied vector. These quantities are calculated from estimated sampled reference phase voltages, which are found out from the stator current error ripple and the parameters of the induction motor. Whenever the actual current error space vector crosses the reference CESV tra¬jectory, an appropriate vector that will force it along the reference trajectory is switched. Extensive study of the proposed controller using vector control is done at different fre¬quencies and transient conditions. This controller has all the advantages of multilevel switching like low dv/dt, lesser electromagnetic interference, lower switch voltage stress and lesser harmonic distortion, in addition to all the dynamic performance advantages of the previous controller. The third work proposes an elegant 5th and 7th order harmonic suppression tech¬nique for open end winding split-phase induction motors, using capacitor fed inverters. Split-phase induction motors have been proposed to reduce the torque and flux ripples of conventional three-phase IM. But these motors have high 5th and 7th order harmonics in the stator windings due to lack of back-emf for these frequencies. A space-vector harmonic analysis of the split-phase IM is conducted and possible 5th and 7th order harmonic sup¬pression techniques studied. A simple harmonic suppression scheme is proposed, which requires the use of only capacitor fed inverters. A PWM scheme that can maintain the capacitor voltage as well as suppress the 5th and 7th order harmonics is also proposed. To test the performance of the proposed scheme, an open-loop v/f control is used on an open-end winding split-phase induction motor under no-load condition. Synchronized PWM with two samples per sector was used, for frequencies above 10 Hz. The har¬monic spectra of the phase voltages and currents were computed and compared with the traditional SVPWM scheme, to highlight the harmonic suppression. The concepts were initially simulated in Matlab/Simulink. Experimental verifica¬tion was done using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control tech¬niques presented shall still remain applicable. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the first work the output pins of the DSP was directly used to drive the inverter switches through a dead-band circuit. For the other two works, DSP outputs the sector information and the PWM signals. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. An FPGA (XC3S200) was used to translate the sector information and the PWM signals to IGBT gate signal logic. A constant dead-time of 1.5 µs was also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. The phase currents and DC bus voltages were measured using hall-effect sensors. An incremental shaft position encoder was also connected to the motor to measure the angular velocity. The switches were realized using 1200 V, 75 A IGBT half bridge modules.

Orientador: Walmir de Freitas Filho / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-27T18:46:05Z (GMT). No. of bitstreams: 1 Ricciardi_TiagoRodarte_D.pdf: 6633244 bytes, checksum: bcb56f82b62350db77ed247ac2913cc9 (MD5) Previous issue date: 2015 / Resumo: Modelos matemáticos e computacionais precisos dos diversos componentes de um sistema de energia elétrica são importantes para estudos e simulações em um cenário de planejamento e operação da rede elétrica. Dentre os elementos de um sistema de geração, transmissão e distribuição de energia elétrica, as cargas são as que apresentam maiores dificuldades em serem adequadamente representadas. Embora esse tema de pesquisa tenha sido exaustivamente explorado, a modelagem de carga tem recebido renovada atenção do setor produtivo e da academia por uma série de fatores, dentre os quais podemos destacar a proliferação de medidores eletrônicos, o interesse por modelos de novos equipamentos e a necessidade da representação mais fiel do comportamento de diferentes cargas frente a distúrbios no sistema. Esta tese de doutoramento propõe duas contribuições na linha de pesquisa sobre modelagem de carga em sistemas de energia elétrica. A primeira delas trata-se de um método de modelagem de carga baseado em medições e na detecção de distúrbios naturais de tensão. O procedimento proposto emprega medidores eletrônicos simples, que são instalados junto a instalações em sistemas de distribuição com motivo outro que não o de modelagem de carga. A ideia principal é a de utilizar tais medidores para, paralelamente a função que desempenham, fornecer para a concessionária informações sobre modelos de carga, como um subproduto da função principal que desempenham. A segunda contribuição proposta é na linha da modelagem de carga baseada em templates, uma técnica recentemente proposta na literatura para modelagem dinâmica de cargas industriais de grande porte. Nesta tese é proposto um modelo dinâmico simplificado de motores de velocidade variável controlados via conversores eletrônicos (Variable Frequency Drives ¿ VFDs), o qual é baseado em um modelo modificado de um motor de indução. O modelo proposto é adequado ao contexto da estrutura de modelagem de cargas industriais proposta pela técnica de modelagem baseada em templates e pode ser facilmente agregado e analisado em programas de simulação por parte de usuários sem necessidades de alterações do código fonte / Abstract: Accurate mathematical and computational models from various electric power systems components are important in a scenario of power systems studies and simulations for grid planning and operation. Among the elements in the electricity generation, transmission and distribution systems, the loads are probably the most difficult ones to be accordingly represented. Though this research topic has been exhaustively explored, there is a renewed interest in industry and academia for power systems load modeling, due to several reasons, including the proliferation of smart meters, the appearance of non-conventional types of load and the continuing need for even more confident representation of different load response for system disturbances. This Ph.D. thesis proposes two contributions to power systems load modeling research field. The first one deals with a load modeling method based on measurements and the detection of natural voltage disturbances. The proposed scheme uses simple smart meters, installed close to customers with a main goal other than load modeling. The main idea is to use data provided by those meters to, in parallel to the main function performed by this device, provide to the utility information regarding load models, as a byproduct capable to add value to the investment in this meters. The second contribution is in the template based load modeling, a recently methodology proposed for dynamic modeling of large industrial facilities. In this thesis, a simplified Variable Frequency Drive (VFD) dynamic model is proposed, which one is based on a modified induction machine model. The proposed model is suitable to the dynamic load model structure proposed by the template based methodology and can be easily aggregated and analyzed in simulation software by basic users without the need of programming a complex model / Doutorado / Energia Eletrica / Doutor em Engenharia Elétrica

Our society moves towards digitalization and the industry is not an exception. Siemenshas developed a wireless condition monitoring device called Simotics Connect in order tohelp them to move forward in the world of digitalization. The Simotics Connect has threeinbuilt sensors. One for temperature, one for vibrations and one for magnetic flux density,a product that is new in the market. This master thesis has investigated its usability forthird party motors, which has not been done.Four areas were investigated, the status in the current market, creating a motorgeometry estimation based on nameplate data, presenting a temperature model to calculatea motor’s cross section temperature and, finally, proposed a stator current model using themagnetic field measurement.Market research has shown that a space for the Simotics Connect to thrive in mostdefinitely exists.The motor geometry estimation, that is based on preliminary electromagnetic sizing,creates a digital twin for the motor that has sufficient accuracy as a tool when calculatinge.g. temperature calculations but lacks accuracy for more advanced and sensitivecalculations e.g for magnetic flux density measurement usability.The temperature model that is presented shows great accuracy when calculating thecross section temperature in the stator but the accuracy decreases for the cross sectiontemperature in the rotor.A stator current model is proposed using a proportional relationship between themagnetic flux density and stator current. The results indicates a linear relationship, thoughusing the digital twin to calculate the proportional constant were concluded to not beaccurate enough. / Sammhället rör sig idag mot digitalisering och industrin är ej ett undantag. Siemens harutvecklat en trådlös underhållsmätare kallad Simotics Connect för att hjälpa dem strävamot en värld inom digitalisering. Simotics Connect hat tre inbyggda sensorer. En för temperatur,en för vibrationer och en för magnetisk flödestäthet, vilket är nytt på marknaden.Detta masterprojekt har undersökt användningen av Simotics Connect för tredjepartsmotorer,vilket ej har gjorts tidigare.Fyra områden undersöktes, statusen på den nuvarande marknaden, en motorgeometriuppskattningmodellbaserad på namnskylsdata, en temperaturmodell för att beräknamotorns tvärsnittstemperatur och, slutligen, en statorströmmodell som använder sig avmagnetiska flödestäthetsmätningen.Marknadsundersökningen har visat att det finns ett utrymme för Simotics Connectatt blomstra inom på den nuvarande marknaden.Motorns geometriska uppskattning, som är baserad i preliminär elektromagnetiskgeometribestämning, skapar en digital tvilling av motorn som är tillräckligt noggrann föratt aggera som ett verktyg vid t.ex. temperatursberäkningar men saknar noggrannhet förmer avancerade och känsliga beräkningar, t ex för användbarhet inom magnetisk flödestäthetsberäkningar.Temperaturmodellen som presenteras visar stor noggrannhet vid beräkning av statornstvärsnittstemperatur, men noggrannheten minskar för rotorns tvärsnittstemperatur.En statorströmmodell föreslås med ett proportionellt förhållande mellan magnetflödesdensitetenoch statorströmmen. Resultaten indikerar ett linjärt förhållande, men användandetav den digitala tvillingen för att beräkna proportionell konstant konstateras attinte vara tillräckligt noggrann metod.

In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of sub-harmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutral-point-clamped (NPC) inverters, cascaded H-bridge, and flying-capacitor multilevel inverters are some of the popular schemes used for high-power applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter-1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic two-level VSI topology. The inverters used in motor drive applications have to be operated in over-modulation range in order to extract the maximum fundamental output voltage that is possible from the dc-link. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these low-order harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these low-order harmonics and non-linear PWM operation in over-modulation region, frequent over-current fault conditions occur and reliability of the drive is jeopardized. The twelve sided-polygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal space-vector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform. Most of the previous works of dodecagonal space-vector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutral-point voltage fluctuation and the neutral-point voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal space-vector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point charge-balancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors. For the speed control of induction motors, the space-vector PWM scheme is more advantageous than the sine-triangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional space-vector PWM is that the trigonometric operations demand formidable computational efforts and look-up tables. Carrier based, common-mode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. In-formation regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is pro-posed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large look-up tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrier-based methods). The open-end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal space-vector structures relied on induction motors with open-end windings. The main disadvantage of open-end winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter-2 of this thesis uses open-end winding motor with flying-capacitor inverters for the generation of dodecagonal space-vectors, the topology presented in chapter-3 utilizes a cascade connection of flying-capacitors and floating H-bridge cells to generate the same set of voltage space-vectors, thus allowing any standard induction motor as the load. Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage space-vector based multilevel inverter drives. In chapter-4 of the thesis, this aspect is taken into ac-count and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter-2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance. The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a four-pole, 3.7kW, 50Hz, 415V three-phase induction motor was used as the load. Since the PWM ports are limited in a DSP, a field-programmable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the dead-time signals for the power devices also.

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.

Energy usage evaluation and condition monitoring for electric machines are important in industry for overall energy savings. Traditionally these functions are realized only for large motors in wired systems formed by communication cables and various types of sensors. The unique characteristics of the wireless sensor networks (WSN) make them the ideal wireless structure for low-cost energy management in industrial plants. This work focuses on developing nonintrusive motor-efficiency-estimation methods, which are essential in the wireless motor-energy-management systems in a WSN architecture that is capable of improving overall energy savings in U.S. industry. This work starts with an investigation of existing motor-efficiency-evaluation methods. Based on the findings, a general approach of developing nonintrusive efficiency-estimation methods is proposed, incorporating sensorless rotor-speed detection, stator-resistance estimation, and loss estimation techniques. Following this approach, two new methods are proposed for estimating the efficiencies of in-service induction motors, using air-gap torque estimation and a modified induction motor equivalent circuit, respectively. The experimental results show that both methods achieve accurate efficiency estimates within ¡À2-3% errors under normal load conditions, using only a few cycles of input voltages and currents. The analytical results obtained from error analysis agree well with the experimental results. Using the proposed efficiency-estimation methods, a closed-loop motor-energy-management scheme for industrial plants with a WSN architecture is proposed. Besides the energy-usage-evaluation algorithms, this scheme also incorporates various sensorless current-based motor-condition-monitoring algorithms. A uniform data interface is defined to seamlessly integrate these energy-evaluation and condition-monitoring algorithms. Prototype wireless sensor devices are designed and implemented to satisfy the specific needs of motor energy management. A WSN test bed is implemented. The applicability of the proposed scheme is validated from the experimental results using multiple motors with different physical configurations under various load conditions. To demonstrate the validity of the measured and estimated motor efficiencies in the experiments presented in this work, an in-depth error analysis on motor efficiency measurement and estimation is conducted, using maximum error estimation, worst-case error estimation, and realistic error estimation techniques. The conclusions, contributions, and recommendations are summarized at the end.

Multilevel converters have become the direct accepted solution for high power converter applications. They are used in wide variety of power electronic applications like power transmission and distribution, electric motor drives, battery management and renewable energy management to name a few. For medium and high voltage motor drives, especially induction motor drives, the use of multilevel voltage source inverters have become indispensible. A high voltage multilevel inverter could be realized using low voltage switching devices which are easily available and are of low cost. A multilevel inverter generates voltage waveforms of very low harmonic distortion by switching between voltage levels of reasonably small amplitude differences. Thus the dv/dt of the output voltage waveform is small and hence the electromagnetic interference generated is less. Because of better quality output generation, the switching frequency of the multilevel inverters could be reduced to control the losses. Thus, a multilevel converter stands definitely a class apart in terms of performance from a conventional two-level inverter. Many multilevel inverter topologies for induction motor drives are available in the literature. The basic multilevel topologies are the neutral point clamped (NPC) inverter, flying capacitor (FC) inverter and the cascaded H-bridge (CHB) inverter. Various other hybrid multilevel topologies have been proposed by using the basic multilevel inverter topologies. It is also possible to obtain multilevel output by using conventional two-level inverters feeding an open-end winding induction motor from both sides. All the conventional multilevel voltage source inverters generate hexagonal (6 sided polygons) voltage space vector structures. When an inverter with hexagonal space vector structure is operated in the over modulation range, significant low order harmonics are generated in the phase voltage output. Over modulation operation is required for the full utilization of the available DC-link voltage and hence maximum power generation. Among the harmonics generated, the fifth and seventh harmonics are of significant magnitudes. These harmonics generate torque ripple in the motor output and are undesirable in high performance motor drive applications. The presence of these harmonics further creates problems in the closed loop current control of a motor, affecting the dynamic performance. Again, the harmonic currents generate losses in the stator windings. Therefore, in short, the presence of harmonic voltages in the inverter output is undesirable. Many methods have been proposed to eliminate or mitigate the effect of the harmonics. One solution is to operate the inverter at high switching frequency and thereby push the harmonics generated to high frequencies. The stator leakage inductance offers high impedance to the high frequency harmonics and thus the harmonic currents generated are negligible. But, high switching frequency brings switching losses and high electromagnetic interference generation in the drive system. And also, high switching frequency operation is effective only in the linear modulation range. Another solution is to use passive harmonic filters at the inverter output. For low order harmonics, the filter components would be bulky and costly. The loss created by the filters degrades the efficiency of the drive system as well. The presence of a filter also affects the dynamic performance of the drive system during closed loop operation. Special pulse width modulation (PWM) techniques like selective harmonic elimination (SHE) PWM can prevent the generation of a particular harmonic from the phase voltage output. The disadvantages of such schemes are limited modulation index, poor dynamic performance and extensive offline computations. An elegant harmonic elimination method is to generate a voltage space vector structure having more number of sides like a dodecagon (12 sided polygons) or an octadecagon (18 sided polygons) rather than a hexagon. Inverter topologies generating dodecagonal voltage space vector structure eliminate fifth and seventh order harmonics, represented as 6n 1; n = odd harmonics, from the phase voltages and hence from the motor phase currents, throughout the entire modulation range. The first harmonics appearing the phase voltage are the 11th and 13th harmonics. Another advantage is the increased linear modulation range of operation for a given DC-link voltage, because geometrically dodecagon is closer to circle than a hexagon. An octadecagonal structure eliminates the 11th and 13th harmonics as well from the phase voltage output. The harmonics present in the phase voltage are of the order 18n 1; n = 1; 2; 3; :::. Thus the total harmonics distortion (THD) of the phase voltage is further improved. The linear modulation range also gets enhanced compared to hexagonal and dodecagonal structures. Multilevel dodecagonal and octadecagonal space vector structures combines the advantages of both multilevel structure and dodecagonal and octadecagonal structure and hence are very attractive solutions for high performance induction motor drive schemes. Chapter 1 of this thesis introduces the multilevel in-verter topologies generating hexagonal, dodecagonal and octadecagonal voltage space vector structures. Inverter topologies generating multilevel dodecagonal and octadecago-nal voltage space vector structures have been proposed before but using multiple DC sources delivering active power. The presence of more than one DC source in the inverter topology makes the back to back operation (four-quadrant operation) of the drive system difficult. And also the drive system becomes more costly and bulky. This thesis proposes induction motor drive schemes generating multilevel dodecagonal and octadecagonal volt-age space vector structures using a single DC source. In Chapter 2, an induction motor drive scheme generating a six-concentric multilevel dodecagonal voltage space vector structure using a single DC source is proposed for an open-end winding induction motor. In the topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a DC source (Vdc) which delivers the entire active power, whereas the secondary inverter DC-link is maintained by a capacitor at a voltage of 0:289Vdc, which is self-balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small DC-link voltage. Hence, switching losses are small for both primary and secondary inverters. An open-loop V/f scheme was used to test the topology and modulation scheme. In the work proposed in Chapter 3, the topology and modulation scheme used in the first work is modified for a star connected induction motor. Again, the scheme uses only a single DC source and generates a six-concentric multilevel space vector struc-ture. The power circuit topology is realized using a three-level flying capacitor (FC) inverter cascaded with an H-bridge (CHB). The capacitors in the CHB inverter are maintained at a voltage level of 0:1445Vdc. The FC inverter switches between volt-age levels of [Vdc; 0:5Vdc; 0] and the CHB inverter switches between voltage levels of [+01445Vdc; 0; 0:1445Vdc]. The PWM scheme generates a quasi-square waveform output from the FC inverter. This results in very few switchings of the FC inverter in a funda-mental cycle and hence the switching losses are controlled. The CHB inverter switches Ch. 0: at high frequency compared to the FC inverter and cancels the low order harmonics (6n 1; n = odd) generated by the FC inverter. Even though the CHB operates at higher switching frequency, the switchings are at low voltage thereby controlling the losses. The linear modulation range of operation is extended to 48:8Hz for a base frequency of 50Hz. An open-loop V/f scheme was used to test the topology and modulation scheme. In Chapter 4, a nine-concentric multilevel octadecagonal space vector structure is proposed for the first time, again using a single DC source. The circuit topology remains same as the work in Chapter 3, except that the CHB capacitor voltage is maintained at 0:1895Vdc. The 5th; 7th; 11th and 13th harmonics are eliminated from the phase voltage output. The linear modulation range is enhanced to 49:5Hz for a base speed of 50Hz. An open-loop V/f scheme and rotor field oriented control scheme were used to test the proposed drive system. All the proposed drive schemes have been extensively simulated and tested in hard-ware. Simulation was performed in MATLAB-SIMULINK environment. For implement-ing the inverter topology, SKM75GB12T4 IGBT modules were used. The control al-gorithms were implemented using a DSP (TI’s TMS320F28334) and an FPGA (Xilinx Spartan XC3S200). A 1kW , 415V , 4-pole induction motor was used for the experiment purpose. The above mentioned induction motor drive schemes generate phase voltage outputs in which the low order harmonics are absent. The linear modulation range is extended near to the base frequency of operation compared to hexagonal space vector structure. In the inverter topologies, the secondary inverters or the CHB inverters functions as harmonic filters and delivers zero active power. The primary inverter in the topologies switches at low frequency, reducing the power loss. Single DC source requirement brings down the cost of the system as well as permitting easy four-quadrant operation. This is also advantageous in battery operated systems like EV applications. With these features and advantages, the proposed drive schemes are suitable for high performance, medium voltage induction motor drive applications.

IGBT based power converters acts as front end in the present day Adjustable Speed Drive (ASD). This offers many advantages and makes regenerative action possible. PWM rectifier operation produces electrically noisy DC bus on common mode basis. This results in higher ground current as compared to three phase diode bridge rectifier. Due to fast turn-ON and turn-OFF time of IGBT, the inverter output voltage dv/dt is high during switching transients and voltage waveform is rich in harmonics. As a result, in applications involving long cable the motor terminal voltage during the switching transient is as high as twice the applied voltage. This voltage stress reduces the life of insulation in motors. The high dv/dt output voltage applied at the motor terminal excites the parasitic capacitive coupling resulting in increased ground currents and causes Electric Discharge Machining (EDM) which reduces the life of motor bearings. The common mode voltage due to PWM rectifier and the inverter appear at the motor terminals exacerbating these problems. The common mode voltage due to PWM inverter with PWM rectifier is analyzed. An integrated approach for filter design is proposed wherein the adverse effects due to common mode voltage of both AFE converter and the inverter is addressed. The proposed topology addresses the problems of common mode voltage, common mode current and voltage doubling due to ASD. The design procedure for proposed filter topology is discussed with experimental results that validate the effectiveness of the filter. Inclusion of such higher order filter in the converter topology leads to problems such as resonance. Passive methods are investigated for damping the line resonance due to LCL filter and common mode resonance due to common mode filter. The need for active damping technique for resonance due to common mode filter is presented. State space based damping technique is proposed to effectively damp the resonance due to line filter and the common mode filter. Experimental results are presented that validate the effectiveness of active damping both on the line basis (differential mode) and line to ground basis (common mode) of the filter.

MULTILEVEL inverters are the preferred choice of converters for electronic power conversion for high power applications. They are gaining popularity in variety of industrial applications including electric motor drives, transportation, energy management, transmission and distribution of power. A large portion of energy conversion systems comprises of multilevel inverter fed induction motor drives. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low. In conventional two level inverters, to get nearly sinusoidal phase current waveform, the switching frequency of the inverter is increased and the harmonics in the currents are pushed higher in the frequency spectrum to reduce the size and cost of the filters. But higher switching frequency has its own drawbacks – in particular for medium voltage, high power applications. They cause large dv_/ dt stresses on the motor terminals and the switching devices, leading to increased electromagnetic interference (EMI) problems and higher switching losses. Harmonics in the motor currents can further be minimized by adopting dodecagonal voltage space vector (SV) switching (12-sided polygon). In case of dodecagonal SV switching, the fifth and seventh order (6n , 1, n = odd) harmonics are completely eliminated for the full modulation range including over modulation and twelve step operation in the motor phase voltages and currents. In addition to low order harmonic current suppression, the linear modulation range for dodecagonal SV switching is also more by 6% when compared to that of the conventional hexagonal SV switching. The dodecagonal voltage SV structure is made possible by connecting two inverters with DC-link voltages Vd and 0:366Vd on either side of an open-end winding induction motor. The dodecagonal space vector switching can be used to produce better quality phase voltage and current waveforms and overcome the problem of low order fifth and seventh harmonic currents and to improve the range for linear modulation while reducing the switching frequency of the inverters when compared to that of the conventional hexagonal space vector based inverters. This thesis focuses on three aspects of multilevel dodecagonal space vector structures (i) Two new power circuit topologies that generate a multilevel dodecagonal voltage space vector structure with symmetric triangles, (ii) A multilevel dodecagonal SV structure with nineteen concentric dodecagons, (iii) Pulse width modulation (PWM) timing calculation methods for a general N-level dodecagonal SV structure. (i) Two new power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles with minimum number of DC link power supplies and floating capacitor H-bridges are proposed. The first power topology is composed of two hybrid cascaded five level inverters connected to either side of an open end winding induction machine. Each inverter consists of a three level neutral point clamped (NPC) inverter, cascaded with an isolated capacitor fed H-bridge making it a five level inverter. The second topology is a hybrid topology for a normal induction motor (star or delta connected), where the power is fed to the motor only from one side. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of the dodecagonal voltage space vector structure. Both topologies have inherent capacitor balancing for floating H-bridges for all modulation indices including transient operations. The proposed topologies do not require any pre-charging circuitry for startup. PWM timing calculation method for space vector modulation is also explored in this chapter. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any iterative searching, off-line computation, look-up tables or angle estimation. Experimental results for steady state operation and transient operation are also presented to validate the proposed concept. (ii) A multilevel dodecagonal voltage space vector structure with nineteen concentric do-decagons is proposed for the first time. This space vector structure is achieved by connecting two sets of asymmetric hybrid five level inverters on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of DC-link voltages and switching states of the inverters. In addition to that, a generic and simple method for calculation of PWM timings using only sampled reference values (v and v ) is proposed. This enables the scheme to be used for any closed loop application like vector control. Also, a new switching technique is proposed which ensures minimum switching while eliminating the fifth and seventh order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady state operation, transient operation including start-up have been presented and the results of Fast Fourier Transform (FFT) analysis is also presented for validating the proposed concept. (iii) A method to obtain PWM timings for a general N-level dodecagonal voltage space vector structure using only sampled reference values is proposed. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle, to get the timings T1 and T2 using trigonometric calculations. This method requires look-up tables and is difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle. The proposed method is generic and can be extended to any number of levels with symmetric structures and does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. The algorithm outputs the triangle number and the PWM timing values of T0, T1 and T2 which can be set as the compare values for any carrier based PWM module to obtain space vector PWM like switching sequences. Simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method. A 3.7 kW, 415 V, 50 Hz, 4-pole open-end winding induction motor was used for the experimental studies. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V insulated-gate bipolar transistor (IGBT) half-bridge modules (SKM75GB12T4). Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz was used. For modulation frequencies 10 Hz and below, a constant sampling frequency of 1 kHz was used as the frequency modulation ratio is high. For modulation frequencies above 10 Hz, synchronous PWM strategy was used. The time duration Ts is the sampling interval for which the timings T1 , T2 and T0 are calculated. As in the case of any synchronous PWM method, the duration of sampling time (Ts) is a function of the fundamental frequency of the modulating signal. In this case, Ts = 1_.fm • 12n) sec. where fm is fundamental frequency in Hertz and ‘n’ is the number of samples per 30ý dodecagonal sector. The PWM timings and the triangle data (from the DSP) is fed to field programmable gate array (FPGA) (SPARTAN XC3S200) clocked at 50 MHz where the actual gating pulses are generated. The capacitor balancing algorithm and the dead-time modules were implemented within FPGA. No external hardware was used for generation of dead-time. The dead-time block generates a constant dead-time of 2 s for all the switches. Extensive testing was done for steady state operations and transient operations including quick acceleration and start-up to validate the proposed concepts. With the advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range, suppression of eleventh and thirteenth harmonics in phase voltages and currents, reduced device voltage ratings, lesser dv_dt stresses on devices and motor phase windings, lower switching frequency, inherent cascaded H-bridge (CHB) capacitor balancing, the proposed space vector structures, the inverter power circuit topologies, the switching techniques and the PWM timing calculation methods can be considered as viable schemes for medium voltage, high power motor drive applications.