It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2019, with the IC feature size shrinking to about 10nm, off-chip interconnects in an area array format will require a pitch of 95 µm. Also, as the industry adopts porous low-K dielectric materials, it is important to ensure that the stresses induced by the off-chip interconnects and the package do not crack or delaminate the low-K material. Compliant free-standing structures used as off-chip interconnects are a potential solution. However, there are several design, fabrication, assembly and integration research challenges and gaps with the current suite of compliant interconnects. Accordingly, as part of this research a unique parallel-path approach has been developed which enhances the mechanical compliance of the compliant interconnect without compromising the electrical parasitics. It also provides for redundancy and thus results in more reliable interconnects. Also, to meet both electrical and mechanical performance needs, as part of this research a variable compliance approach has been developed so that interconnects near the center of the die have lower electrical parasitics while the interconnects near the corner of the die have higher mechanical compliance. Furthermore, this work has developed a fabrication process which will facilitate cost-effective fabrication of free-standing compliant interconnects and investigated key factors which impact assembly yield of free-standing compliant interconnects. Ultimately the proposed approaches are demonstrated by developing an innovative compliant interconnect called FlexConnects. Hence, through this research it is expected that the developed compliant interconnect would address the needs of first level interconnects over the next decade and eliminate a bottleneck that threatens to impede the exponential growth in microprocessor performance. Also, the concepts developed in this research are generic in nature and can be extended to other aspects of electronic packaging.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2008. / Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engfineering and Applied Science, Department of Systems Science and Industrial Engineering, 2009. / Includes bibliographical references.

Laser Induced Forward Transfer (LIFT) techniques show promise as a disruptive technology which will enable the placement of components smaller than what conventional pick-and-place techniques are capable of today. Limitations of current die-attach techniques are presented and discussed and present the opportunity for a new placement method. This study introduces the Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) process and is an application of the unique blistering behavior of a dynamic releasing layer when irradiated by low energy focused UV laser pulses. The potential of tmSLADT as the next generation LIFT technique is demonstrated by the "touchless" transfer of 65 μm thick silicon tiles between two substrates spaced 195 μm apart. Additionally, the advantages of an enclosed blister-actuator mechanism over previously studied ablative and thermal releasing techniques are discussed. Finally, experimental results studying transfer precision indicate this non optimized die transfer process compares with, and may exceed, the placement precision of current assembly techniques. / Defense Microelectronics Activity (DMEA) under agreement number H94003-09-2-0905

In the past decade, there has been an increased interest in low-cost, low-power, high data rate wireless systems for both commercial and defense applications. Some of these include air defense systems, remote sensing radars, and communication systems that are used for unmanned aerial vehicles, ground vehicles, and even the individual consumer. All of these applications require state-of-the-art technologies to push the limits on several design factors such as functionality, weight, size, conformity, and performance while remaining cost effective. There are several potential solutions to accomplish these objectives and a highly pursued path is through the utilization of advanced integrated system platforms with high frequency, versatile, multilayered materials. This work intends to explore advanced 3-D integration for state-of the art components in wireless systems using LCP multilayer organic platforms. Several packaging techniques are discussed that utilize the inherent benefits of this material. Wire bond, via interconnect, and flip-chip packages are implemented at RF and millimeter-wave (mm-wave) frequencies to explore the benefits of each in terms of convenience, reliability, cost, and performance. These techniques are then utilized for the demonstration of bulk acoustic waveguide (BAW) filter applications and for the realization of highly integrated phased-array antenna systems.

This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. In this dissertation, a fine-pitch ball-grid array (FBGA) package, a multichip module (MCM)-L package, and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared to those of inductors monolithically integrated on Si and GaAs substrates. All the inductors are modeled with a physical, simple, equivalent two-port model for the VCO design as well as for phase noise analysis. The losses in an LC-tank are analyzed from the phase noise perspective. For the implementation of VCOs, the effects of the interconnection between the embedded inductor and the VCO circuit are investigated. The VCO using the on-chip inductors is designed as a reference. The performance of VCOs using the embedded inductor in a FBGA and a WLP is compared with that of a VCO using the on-chip inductor. The VCO design is optimized from the high-Q perspective to enhance performance. Through this optimization, less phase noise, lower power consumption, and a wider frequency tuning range are obtained simultaneously.

Wireless communications have been an indispensable aspect of everyday life, and there is an increasing consumer demand for accessing several wireless communication technologies from a single, compact, mobile device. System-on-package (SOP) technology is an advanced packaging technology that has been proven to realize the convergence of multiple functions into miniaturized, high-performance systems to meet this demand. With the advancements in the SOP technology, the miniaturization of the front-end module has been achieved using embedded passives in multilayer packages. However, the integration of the antenna directly on the module package is still the barrier to achieve a fully-integrated, high-performance RF SOP system. The main reason for this missing link is that integrating the antenna on the package requires miniaturizing the antenna, which is a difficult task. The focus of this dissertation is to design high-performance antennas along with developing techniques for miniaturization and system-on-package (SOP) integration of these antennas to achieve fully-integrated SOP systems using advanced multilayer organic substrates and thin-film magneto-dielectric materials. The targeted spectrum for the antenna designs are 2.4/5 GHz WLAN/WiMAX and 60 GHz WPAN bands. Several novel antenna designs and configurations to integrate the antenna on the package along with the module are discussed in this dissertation. The advanced polymers used in this research are Liquid Crystalline Polymer (LCP), RXP, and thin-film magneto-dielectrics.

In our age in which the use of electronic devices is expanding all over the world, their reliability and miniaturization have become very crucial. The thesis is based on the study of one of the most frequent failure mechanisms in semiconductor packages, the delamination of interface or the separation of two bonded materials, in order to improve their adhesion and a fortiori the reliability of microelectronic devices. It focuses on the metal (-oxide) / polymer interfaces because they cover 95% of all existing interfaces. Since several years, research activities at mesoscopic scale (1-10µm) have proved that the more roughened the surface of the interface, i.e., presenting sharp asperities, the better the adhesion between these two materials. Because roughness exhibits extremely complex shapes, it is difficult to find a description that can be used for reliability analysis of interfaces. In order to investigate quantitatively the effect of roughness variation on adhesion properties, studies have been carried out involving analytical fracture mechanics; then numerical studies were conducted with Finite Element Analysis. Both were done in a deterministic way by assuming an ideal profile which is repeated periodically. With the development of statistical and stochastic roughness representation on the one hand, and with the emergence of probabilistic fracture mechanics on the other, the present work adds a stochastic framework to the previous studies. In fact, one of the Stochastic Finite Element Methods, the Perturbation method is chosen for implementation, because it can investigate the effect of the geometric variations on the mechanical response such as displacement field. In addition, it can carry out at once what traditional Finite Element Analysis does with numerous simulations which require changing geometric parameters each time. This method is developed analytically, then numerically by implementing a module in a Finite Element package MSc. Marc/Mentat. In order to get acquainted and to validate the implementation, the Perturbation method is applied analytically and numerically to the 3 point bending test on a beam problem, because the input of the Perturbation method in terms of roughness parameters is still being studied. The capabilities and limitations of the implementation are outlined. Finally, recommendations for using the implementation and for furture work on roughness representation are discussed.

Mixed signal system-on-package (SoP) technology is a key enabler for increasing functional integration, especially in mobile and wireless systems. Due to the presence of multiple dissimilar modules, each having unique power supply requirements, the design of the power distribution network (PDN) becomes critical. Typically, this PDN is designed as alternating layers of power and ground planes with signal interconnects routed in between or on top of the planes. The goal for the simulation of multi-layer power/ground planes, is the following: Given a stack-up and other geometrical information, it is required to find the network parameters (S/Y/Z) between port locations. Commercial packages have extremely complicated stack-ups, and the trend to increasing integration at the package level only points to increasing complexity. It is computationally intractable to solve these problems using these existing methods. The approach proposed in this thesis for obtaining the response of the PDN is the multi-layer finite difference method (M-FDM). A surface mesh / finite difference based approach is developed, which leads to a system matrix that is sparse and banded, and can be solved efficiently. The contributions of this research are the following: 1. The development of a PDN modeler for multi-layer packages and boards called the the multi-layer finite difference method. 2. The enhancement of M-FDM using multi-port connection networks to include the effect of fringe fields and gap coupling. 3. An adaptive triangular mesh based scheme called the multi-layer finite element method (MFEM) to address the limitations of M-FDM 4. The use of modal decomposition for the co-simulation of signal nets with the PDN. 5. The use of a robust GA-based optimizer for the selection and placement of decoupling capacitors in multi-layer geometries. 6. Implementation of these methods in a tool called MSDT 1.

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100 nm near the transistors and 1000 nm away from the transistors close to the solder bumps. In such BEOL layered stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers. This work focuses on developing framework based on cohesive zone modeling approach to study interfacial delamination in sub-micron thick layers. Such a framework is then successfully applied to predict microelectronic device reliability. As intentionally creating pre-fabricated cracks in such interfaces is difficult, this work examines a combination of four-point bend and double-cantilever beam tests to create initial cracks and to develop cohesive zone parameters over a range of mode-mixity. Similarly, a combination of four-point bend and end-notch flexure tests is used to cover additional range of mode-mixity. In these tests, silicon wafers obtained from wafer foundry are used for experimental characterization. The developed parameters are then used in actual microelectronic device to predict the onset and propagation of crack, and the results from such predictions are successfully validated with experimental data. In addition, nanoindenter-based shear test technique designed specifically for this study is demonstrated. The new test technique can address different mode mixities compared to the other interfacial fracture characterization tests, is sensitive to capture the change in fracture parameter due to changes in local trace pattern variations around the vicinity of bump and the test mimics the forces experienced by the bump during flip-chip assembly reflow process. Through this experimental and theoretical modeling research, guidelines are also developed for the reliable design of BEOL stacks for current and next-generation microelectronic devices.