MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.

Multilevel inverters are very popular for medium and high-voltage induction motor (IM) drive applications. They have superior performance compared to 2-level inverters such as reduced harmonic content in output voltage and current, lower common mode voltage and dv/dt, and lesser voltage stress on power switches. To get nearly sinusoidal current waveforms, the switching frequency of the conventional inverters have to be in¬creased. This will lead to higher switching losses and electromagnetic interference. The problem in using lower switching frequency is the introduction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching. Dodecagonal voltage space-vector based multilevel inverters have been proposed as an improvement over the conventional hexagonal space vector based inverters. They achieve complete elimination of 5th and 7th order harmonics throughout the modulation range. The linear modulation range is also extended by about 6.6%, since the dodecagon is closer to circle than a hexagon. The previous works on dodecagonal voltage space vector based VSI fed drives used voltage controlled PWM (VC-PWM). Although these controllers are more popular, they have inferior dynamic performance when compared to current controlled PWM (CC¬PWM). VSIs using current controlled PWM have excellent dynamic response, inherent short-circuit protection and are simple to implement. The conventional CC-PWM tech¬niques have large switching frequency variation and large current ripple in steady-state. xix As a result, there has been significant research interest to achieve current controlled VSI fed IM drives with constant switching frequency. Two current error space vector (CESV) based hysteresis controllers for dodecagonal voltage space-vector based VSI fed induction motor drives are proposed in this work. The proposed controllers achieve nearly constant switching frequency at steady state operation, similar to VC-SVPWM based VSI fed IM drives. They also have fast dynamic response while at the same time achieving complete elimination of fifth and seventh order harmonics for the entire modulation range, due to dodecagonal voltage vector switching. The first work proposes a nearly constant switching frequency current error space vector (CESV) based hysteresis controller for an IM drive with single dodecagonal voltage space vectors. Parabolic boundaries computed offline are used in the proposed controller. An open-end winding induction motor is fed from two inverters with asymmetrical DC link voltages, to generate the dodecagonal voltage space vectors. The drive scheme is first studied at different frequencies with a space vector based PWM (SVPWM) control, to obtain the current error space vector boundaries. The CESV boundary at each frequency can be approximated with four parabolas. These parabolic boundaries are used in the proposed controller to limit the CESV trajectory. Due to symmetries in the parabolas only two set of parabola parameters, at different frequencies, need to be stored. A generalized next vector selection logic, valid for all sectors and rotation direction, is used in the proposed controller. For this an axis transformation is done in all sectors, to bring the CESV trajectory to the first sector. The sector information is obtained from the estimated fundamental stator phase voltage. The proposed controller is extensively studied using vector control at different frequencies and transient conditions. This controller maintains nearly constant switching frequency at steady state operation, similar to VC-SVPWM inverters, while at the same time achieving better dynamic performance and complete elimination of 5th and 7th order harmonics throughout the modulation range. In the second work the nearly constant switching frequency current hysteresis con¬troller is extended to multilevel dodecagonal voltage space-vector based IM drives, with online computation of CESV boundaries. The multilevel dodecagonal space-vector dia¬gram has different types of triangles, and the previously proposed methods for multilevel hexagonal VSI based current hysteresis controllers cannot be used directly. The CESV trajectory of the VC-SVPWM, obtained for present triangular region, is used as the reference trajectory of the proposed controller. The CESV reference boundaries are com¬puted online, using switching dwell time and voltage error vector of each applied vector. These quantities are calculated from estimated sampled reference phase voltages, which are found out from the stator current error ripple and the parameters of the induction motor. Whenever the actual current error space vector crosses the reference CESV tra¬jectory, an appropriate vector that will force it along the reference trajectory is switched. Extensive study of the proposed controller using vector control is done at different fre¬quencies and transient conditions. This controller has all the advantages of multilevel switching like low dv/dt, lesser electromagnetic interference, lower switch voltage stress and lesser harmonic distortion, in addition to all the dynamic performance advantages of the previous controller. The third work proposes an elegant 5th and 7th order harmonic suppression tech¬nique for open end winding split-phase induction motors, using capacitor fed inverters. Split-phase induction motors have been proposed to reduce the torque and flux ripples of conventional three-phase IM. But these motors have high 5th and 7th order harmonics in the stator windings due to lack of back-emf for these frequencies. A space-vector harmonic analysis of the split-phase IM is conducted and possible 5th and 7th order harmonic sup¬pression techniques studied. A simple harmonic suppression scheme is proposed, which requires the use of only capacitor fed inverters. A PWM scheme that can maintain the capacitor voltage as well as suppress the 5th and 7th order harmonics is also proposed. To test the performance of the proposed scheme, an open-loop v/f control is used on an open-end winding split-phase induction motor under no-load condition. Synchronized PWM with two samples per sector was used, for frequencies above 10 Hz. The har¬monic spectra of the phase voltages and currents were computed and compared with the traditional SVPWM scheme, to highlight the harmonic suppression. The concepts were initially simulated in Matlab/Simulink. Experimental verifica¬tion was done using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control tech¬niques presented shall still remain applicable. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the first work the output pins of the DSP was directly used to drive the inverter switches through a dead-band circuit. For the other two works, DSP outputs the sector information and the PWM signals. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. An FPGA (XC3S200) was used to translate the sector information and the PWM signals to IGBT gate signal logic. A constant dead-time of 1.5 µs was also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. The phase currents and DC bus voltages were measured using hall-effect sensors. An incremental shaft position encoder was also connected to the motor to measure the angular velocity. The switches were realized using 1200 V, 75 A IGBT half bridge modules.

No description available.

In industrial settings, a common challenge associated with electrical machines is the lack of parameters, which are not always available from the machine manufacturer. These parameters play a crucial role in tuning the control gains of Field-Oriented Control (FOC). Traditional parameter identification methods, widely accepted in the literature, are the standard IEEE tests such as DC measurement, no-load test, locked-rotor test, and short circuit test. However, their implementation can be impractical as they necessitate additional equipment that may be costly and not readily accessible. This thesis addresses self-commissioning procedures as a solution to this challenge, aiming to automatically identify electrical parameters of machine equivalent circuits. Specifically, this study focuses on the Imperix motor testbench, comprising Induction Machine (IM) and Surface Mounted Permanent Magnet Synchronous Machine (SPMSM). Self-commissioning utilizes signal injection through a power converter and the available sensors, with minimal operator intervention and no additional equipment. For the SPMSM, the parameters under study include the stator resistance, the synchronous inductance, and the Permanent Magnets (PM)-flux. The resistance is estimated through DC current injection considering the inverter non-linearity. The synchronous inductance and its saturation characteristic are examined using high-frequency sinusoidal injection with and without DC bias via a Current Controller (CC), and square wave voltage injection through hysteresis control. The PM-flux is determined by accelerating the SPMSM using the IM as a prime mover in an open circuit configuration. This deviation from the standstill constraint of the self-commissioning procedure is necessary as the PM’s effect becomes visible only when the rotor speed is non-zero. For the IM, the stator resistance, the leakage inductance, the rotor resistance, and the magnetizing inductance are analyzed. The stator resistance and inverter non-linearity are identified using the same method as for the SPMSM. The leakage inductance is tested with a high-frequency sinusoidal injection with stepped DC bias, with which the saturation characteristic is built. Then, a DC-biased low-frequency sinusoidal injection identifies the rotor resistance. The magnetizing inductance is not identified in this work because of the extensive nature of the problem and time constraints. Comparison with standard IEEE tests serves as validation, demonstrating close alignment of the results, except for discrepancies in the unsaturated SPMSM synchronous inductance estimation. The introduced innovation involves adapting existing procedures, initially developed for other AC machines, to SPMSM applications, for which only limited literature is available. Overall, this work makes a valuable contribution to understanding the influence of inverter non-linearity and saturation behavior on parameter identification. It also opens the door to integrating saturation effects into control algorithms, which enables dynamic adjustment of FOC gains, potentially enhancing control performance. / I industriella miljöer är en vanlig utmaning i samband med elektriska maskiner bristen på parametrar, som inte alltid är tillgängliga från maskintillverkaren. Dessa parametrar spelar en avgörande roll för att ställa in kontrollförstärkningarna för fältorienterad kontroll (FOC). Traditionella metoder för parameteridentifiering, som är allmänt accepterade i litteraturen, är standard IEEE-tester som DC-mätning, nollbelastningstest, låst rotortest och kortslutningstest. Implementeringen av dessa kan dock vara opraktisk eftersom de kräver ytterligare utrustning som kan vara kostsam och svåråtkomlig. Denna avhandling behandlar procedurer för självavstängning som en lösning på denna utmaning och syftar till att automatiskt identifiera elektriska parametrar för maskinens ekvivalenta kretsar. Studien fokuserar särskilt på Imperix motortestbänk, som består av induktionsmaskiner (IM) och ytmonterad synkronmaskin med permanentmagnet (SPMSM). Självinkoppling är en stilleståndsprocedur som använder signalinjektion genom en kraftomvandlare och de tillgängliga sensorerna, med minimal operatörsintervention och utan extra utrustning. För SPMSM studeras parametrarna statorresistans, synkroninduktans och permanentmagneter (PM)-flöde. Motståndet uppskattas genom likströmsinjektion med hänsyn till växelriktarens olinjäritet. Den synkrona induktansen och dess mättnadskarakteristik undersöks med hjälp av högfrekvent sinusinjektion med och utan DC-bias via en strömstyrenhet (CC), och fyrkantsvåginjektion genom hysteresstyrning. Flödet PM bestäms genom acceleration av SPMSM med hjälp av IM som drivmotor i en öppen kretskonfiguration. Denna avvikelse från stilleståndsbegränsningen i förfarandet för självavstängning är nödvändig eftersom PM effekt blir synlig först när rotorhastigheten är skild från noll. För IM analyseras statorresistansen, läckinduktansen, rotorresistansen och den magnetiserande induktansen. Statorresistansen och inverterns olinjäritet identifieras med samma metod som för SPMSM. Läckageinduktansen testas med en högfrekvent sinusformad injektion med stegad DC-bias, med vilken mättnadskarakteristiken byggs. Därefter identifierar en DC-baserad lågfrekvent sinusinjektion rotorresistansen. Den magnetiserande induktansen identifieras inte i detta arbete på grund av problemets omfattande natur och tidsbegränsningar. Jämförelse med standard IEEE-tester fungerar som validering och visar att resultaten ligger nära varandra, med undantag för avvikelser i uppskattningen av den omättade synkrona induktansen för SPMSM. Den introducerade innovationen innebär att befintliga procedurer, som ursprungligen utvecklats för andra AC-maskiner, anpassas till SPMSM-tillämpningar, för vilka endast begränsad litteratur finns tillgänglig. Sammantaget ger detta arbete ett värdefullt bidrag till förståelsen av hur omriktarens icke-linjäritet och mättnadsbeteende påverkar parameteridentifieringen. Det öppnar också dörren för att integrera mättnadseffekter i regleralgoritmer, vilket möjliggör dynamisk justering av FOC-förstärkningar, vilket potentiellt kan förbättra reglerprestanda.

In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of sub-harmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutral-point-clamped (NPC) inverters, cascaded H-bridge, and flying-capacitor multilevel inverters are some of the popular schemes used for high-power applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter-1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic two-level VSI topology. The inverters used in motor drive applications have to be operated in over-modulation range in order to extract the maximum fundamental output voltage that is possible from the dc-link. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these low-order harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these low-order harmonics and non-linear PWM operation in over-modulation region, frequent over-current fault conditions occur and reliability of the drive is jeopardized. The twelve sided-polygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal space-vector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform. Most of the previous works of dodecagonal space-vector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutral-point voltage fluctuation and the neutral-point voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal space-vector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point charge-balancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors. For the speed control of induction motors, the space-vector PWM scheme is more advantageous than the sine-triangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional space-vector PWM is that the trigonometric operations demand formidable computational efforts and look-up tables. Carrier based, common-mode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. In-formation regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is pro-posed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large look-up tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrier-based methods). The open-end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal space-vector structures relied on induction motors with open-end windings. The main disadvantage of open-end winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter-2 of this thesis uses open-end winding motor with flying-capacitor inverters for the generation of dodecagonal space-vectors, the topology presented in chapter-3 utilizes a cascade connection of flying-capacitors and floating H-bridge cells to generate the same set of voltage space-vectors, thus allowing any standard induction motor as the load. Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage space-vector based multilevel inverter drives. In chapter-4 of the thesis, this aspect is taken into ac-count and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter-2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance. The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a four-pole, 3.7kW, 50Hz, 415V three-phase induction motor was used as the load. Since the PWM ports are limited in a DSP, a field-programmable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the dead-time signals for the power devices also.

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.

In high power induction motor drives, the switching frequency of the inverter is quite low due to the high losses in the power devices. Real-time PWM strategies, which result in reduced harmonic distortion under low switching frequencies and have maximum possible DC bus utilisation, are developed for such drives in the present work. The space vector approach is taken up for the generation of synchronised PWM waveforms with 3-Phase Symmetry, Half Wave Symmetry and Quarter Wave Symmetry, required for high-power drives. Rules for synchronisation and the waveform symmetries are brought out. These rules are applied to the conventional and modified forms of space vector modulation, leading to the synchronised conventional space vector strategy and the Basic Bus Clamping Strategy-I, respectively. Further, four new synchronised, bus-clamping PWM strategies, namely Asymmetric Zero-Changing Strategy, Boundary Sampling Strategy-I, Basic Bus Clamping Strategy-II and Boundary Sampling Strategy-II, are proposed. These strategies exploit the flexibilities offered by the space vector approach like double-switching of a phase within a subcycle, clamping of two phases within a subcycle etc. It is shown that the PWM waveforms generated by these strategies cannot be generated by comparing suitable 3-phase modulating waves with a triangular carrier wave. A modified two-zone approach to overmodulation is proposed. This is applied to the six synchronised PWM strategies, dealt with in the present work, to extend the operation of these strategies upto the six-step mode. Linearity is ensured between the magnitude of the reference and the fundamental voltage generated in the whole range of modulation upto the six-step mode. This is verified experimentally. A suitable combination of these strategies leads to a significant reduction in the harmonic distortion of the drive at medium and high speed ranges over the conventional space vector strategy. This reduction in harmonic distortion is demonstrated, theoretically as well as experimentally, on a constant V/F drive of base frequency 50Hz for three values of maximum switching frequency of the inverter, namely 450Hz, 350Hz and 250Hz. Based on the notion of stator flux ripple, analytical closed-form expressions are derived for the harmonic distortion due to the different PWM strategies. The values of harmonic distortion, computed based on these analytical expressions, compare well with those calculated based on Fourier analysis and those measured experimentally.

Multilevel inverter technology has emerged recently as a very important alternative in the area of high-power medium-voltage energy control. Voltage operation above semiconductor device limits, lower common mode voltages, near sinusoidal outputs together with small dv/dt’s, are some of the characteristics that have made this power converters popular for industry and modern research. However, the existing solutions suffer from some inherent drawbacks like common mode voltage problem, DC-link capacitor voltage fluctuation etc. Cascaded multi-level inverter with open-end winding induction motor structure promises significant improvements for high power medium-voltage applications. This dissertation investigates such cascaded multi-level inverters for open-end winding induction motor drive with reduced switch count. Similar to the conventional two-level inverters, other multi-level inverters with PWM control generate alternating common mode voltage (CMV). The alternating common mode voltage coupled through the parasitic capacitors in the machine and results in excessive bearing current and shaft voltage. The unwanted shaft voltage may cross the limit of insulation breakdown voltage and cause motor failure. This alternating common mode voltage adds to the total leakage current through ground conductor and acts as a source of conducted EMI which can interfere with other electronic equipments around. As the number of level increase in the inverter, different voltage levels are made available by using DC-link capacitor banks, instead of using different isolated power supplies. The intermediate-circuit capacitor voltages which are not directly supplied by the power sources are inherently unstable and require a suitable control method for converter operation, preferably without influence on the load power factor. Apart from normal operation, the sudden fault conditions may occur in the system and it is necessary to implement the control strategy considering this condition also. A five-level inverter topology with cascaded power circuit structure is proposed in this dissertation with the strategy to eliminate the common mode voltage and also to maintain the balance in the DC-link capacitor voltages. The proposed scheme is based on a dual five-level inverter for open-end winding induction motor. The principle achievement of this work is the reduction of power circuit complexity in the five-level inverter compared to a previously proposed five-level inverter structure for open-end winding IM drive with common mode voltage elimination. The reduction in the number of power switching devices is achieved by sharing the two two-level inverters for both the inverter structures. The resultant inverter structure can produce a nine-level voltage vector structure with the presence of alternating common mode voltage. The inverter structure is formed by cascading conventional two-level inverters together with NPC three-level inverters. Thus it offers modular and simpler power bus structure. As the power circuit is realised by cascading conventional two-level and NPC three-level inverters the number of power diodes requirements also reduced compared to the conventional NPC five-level inverters. The present proposed structure is implemented for the open-end winding induction motor and the power circuit offers more number of switching state redundancies compared to any conventional five-level inverter. The inverter structure required half the DC-link voltage compared to the DC-link voltage required for the conventional five-level inverter structure for induction motor drive and this reduces the voltage stress on the individual power devices. The common mode voltage is eliminated by selecting only the switching states which do not generate any common mode voltage in pole voltages hence there will be no common mode voltage at the motor phase also. The technique of using the switching state selection for the common mode voltage elimination, cancels out the requirement of the filter for the same purpose. As the inverter output is achieved without the presence of common mode voltage, the dual inverter can be fed from the common DC-link sources, without generating any zero sequence current. Hence the proposed dual five-level inverter structure requires only four isolated DC supplies. The multi-level inverters supplied by single power supply, have inherent unbalance in the DC-link capacitor voltages. This unbalance in the DC-link capacitor voltages causes lower order harmonics at the inverter output, resulting in torque pulsation and increased voltage stress on the power switching devices. A five-level inverter with reduced power circuit complexity is proposed to achieve the dual task of eliminating common mode voltage and DC-link capacitor voltage balancing. The method includes the analysis of current through the DC-link capacitors, depending on the switching state selections. The conditions to maintain all the four DC-link capacitor voltages are analysed. In an ideal condition when there is no fault in the power circuit the balance in the capacitor voltages can be maintained by selecting switching states in consecutive intervals, which have opposite effect on the capacitor voltages. This is called the open loop control of DC-link capacitor voltage balancing, since the capacitor voltages are not sensed during the selection of the switching states. The switching states with zero common mode voltages are selected for the purpose of keeping the capacitor voltages in balanced condition during no fault condition. The use of any extra hardware is avoided. The proposed open loop control of DC-link capacitor voltage balancing is capable of keeping the DC-link capacitor voltages equal in the entire modulation region irrespective of the load powerfactor. The problem with the proposed open loop control strategy is that, it can not take any corrective action if there is any initial unbalance in the capacitor voltages or if any unbalance occurs in the capacitor voltages during operation of the circuit,. To get the corrective action in the capacitor voltages due occurrence of any fault in the circuit, the strategy is further improved and a closed loop control strategy for the DC-link capacitor voltages is established. All the possible fault conditions in the four capacitors are identified and the available switching states are effectively used for the corrective action in each fault condition. The strategy is implemented such a way that the voltage balancing can be achieved without affecting the output fundamental voltage. The proposed five-level inverter structure presented in this thesis is based on a previous work, where a five-level inverter structure is proposed for the open-end winding induction motor. In that previous work 48 switches are used for the realization of the power circuit. It is observed that all the available switching states in this previous work are not used for any of the performance requirement of CMV elimination or DC-link voltage balancing. So, in this proposed work, the power circuit is optimized by reducing some of the switches, keeping the performance of the inverter same as the power circuit proposed in the previous work. The five-level inverter proposed in this thesis used 36 switches and the number of switching states is also reduced. But, the available switching states are sufficient for the CMV elimination and DC-link capacitor voltage balancing. The advantage of the modular circuit structure of this proposed five-level inverter is further investigated and the inverter structure is modified to a seven-level inverter structure for the open end winding induction motor. The proposed power circuit of the seven-level inverter uses only 48 switches, which is less compared to any seven-level inverter structure for the open end winding induction motor with common mode voltage elimination. The power circuit is reduced by sharing four two-level inverters to both the individual seven-level inverters in both the sides of the of the open end winding induction motor. The cascaded structure eliminates the necessity of the power diodes as required by the conventional NPC multilevel inverters. The proposed seven-level inverter is capable of producing a thirteen-level voltage vector hexagonal structure with the presence of common mode voltage. The common mode voltage elimination is achieved by selecting only the switching states with zero common mode voltage from both the inverters and the combined inverter structure produce a seven-level voltage vector structure with zero common mode voltage. The switching frequency is also reduced for the seven-level inverter compared to the proposed five-level inverter. The advantage of this kind of power circuit structure is that the number of power diode requirement is same in both five-level and seven-level inverters. Since there is no common mode voltage in the output voltages, the dual seven-level inverter structure can be implemented with the common DC-link voltage sources for both the sides. Six isolated power supplies are sufficient for both the seven-level inverters. The available switching states in this proposed seven-level inverter are further analysed to implement the open loop and closed loop capacitor voltage balancing and this allow the power circuit to run with only three isolated DC supplies. All the proposed work presented in this thesis are initially simulated in SIMULINK toolbox and then implemented in a form of laboratory prototype. A 2.5KW open end winding induction motor is used for the implementation of these proposed works. But all these work general in nature and can be implemented for high power drive applications with proper device ratings.

Use of multilevel inverters are inevitable in medium and high voltage drives. This is due to the fact that the multilevel inverters can produce voltages in smaller steps which will reduce the harmonic content and result in more sinusoidal voltages and currents as compared to voltages and currents from two-level inverters. Due to the device limitations, use of two-level inverters is not possible in medium and high voltage drive applications. Though multiple devices can be connected both in series and parallel to achieve two-level operation, the output voltages still suffer from high harmonic content. Multilevel inverters have multiple DC voltage levels with switches that enable one of the voltage steps to be applied to the load. Due to decrease in step size during each switching instant, output voltages and currents of the multilevel inverters have considerably less harmonic content. As the number of levels increase, the switching step reduces thereby the harmonic content also reduces drastically. Due to their advantages, multilevel inverters have gained lot of acceptance in the industry even at lower voltages. The three main configurations that have gained popularity are the neutral point clamped converter, the flying capacitor converter and the cascaded H-bridge converter. Each converter has its own set of advantages and disadvantages. Based on the requirements of various applications, it is possible to fabricate hybrid multilevel topologies that are combinations of the three basic topologies. Researchers around the world have proposed several such converters for diverse applications so as to suit particular requirements like modularity, ease of control, improved reliability, fault tolerant capability etc. The present thesis explores multilevel converters with single DC link to be used for motor drive and grid connected applications. A novel five-level inverter topology formed by cascading a floating capacitor H-bridge module to a regular three-level flying capacitor inverter has been explored in chapter 2. The three-level flying capacitor inverter can generate pole voltages of 0, VDC /2 and VDC . By cascading it with another floating capacitor H-bridge of voltage magnitude VDC /4, pole voltages of 0, VDC /4, VDC/2, 3VDC /4 and VDC . Each of these pole voltage levels can have one or more switching combinations. However each switching combination has a unique effect on the state of the two capacitor voltages. By switching through redundant switching combinations for the same pole voltage, the two capacitors present in each phase can be balanced. The proposed topology also has an advantage that if one of the devices in the H-bridge fails, the topology can still be operated as a regular three-level flying capacitor inverter that can supply full load at rated power by bypassing the faulty H-bridge. This fault tolerant operation of the converter will enable it to be used in applications like traction and marine drives where high reliability is needed. The proposed converter needs a single DC link. All the required voltage levels can be generated from the single DC link. This enables back to back grid connected operation possible where multiple converters can interact with a single DC link. Various pole voltage switching combination and its effect on individual capacitor has been studied. A control algorithm to balance the capacitor voltages by switching through multiple redundancies for the same pole voltage has been developed. The proposed configuration has been implemented in hardware using IGBT H-bridge modules and the control circuitry is realized using DSP and FPGA. The performance of the drive is verified for various frequencies and modulation indices during steady state by running a three phase induction motor at no load. The stability of the drive during transients has been studied by accelerating the machine suddenly at no load and analyzing the performance of the drive. The capacitor voltages are made to deviate from their intended values and the capacitor balancing algorithm has been verified for its ability to bring the capacitor voltages back to their intended values. The experimental results have been presented and discussed in detail in the chapter 2. In the third chapter a common-mode voltage eliminated three-level inverter using a single DC link has been proposed. The power schematic is similar to the one presented in chapter 2. In this chapter the space vector polygon formed by the three phases of the proposed topology has been presented. The common-mode voltage generated by different pole voltage combinations for same space vector location and the redundant switching state combinations has been studied. The pole voltage combinations with zero common mode voltage have been studied. The switching state redundancies for the the pole voltage have been studied. The space vector polygon formed with the pole voltage combinations has been analyzed. A drive is made with the proposed common-mode voltage eliminated inverter. The performance of the drive is tested for various modulation indices and frequencies by running a three phase squirrel cage induction motor at no load. The transient performance is verified by accelerating the motor suddenly and checking the common-mode voltage along with the capacitor voltages. The results have been presented and discussed in detail in chapter 3. This converter has advantages like use of single DC supply, ability to operate as a regular three level converter in case of failure of one of the H-bridges. The work presented in fourth chapter proposes a novel three phase 17-level inverter configuration which utilizes a single DC supply. The rest of voltages are generated using three floating capacitor H-bridges. The redundant switching combinations for generating various pole voltages and their effect on the capacitors have been studied and suitable capacitor balancing algorithm has been developed. The proposed topology has been realized in hardware and the performance of the drive during steady state has been studied by running an induction motor at various modulation indices and frequencies. The transient response of the drive has been observed by accelerating the motor suddenly under no load. The results have been presented in detail in chapter four. This configuration also needs a single DC link. The advantages of this configuration is in case of failure of any devices in the H-bridge, the drive can be operated at reduced number of levels while supplying full load current. This feature helps the drive to be used in fault tolerant applications like marine and traction drives where reliability of the drive is of prime importance. All the topologies that have been presented in the previous chapters have mentioned about the usage of the proposed genre of topologies use single DC link and hence will enable back to back grid tied inverter connection. In the fifth chapter this has has been verified experimentally. The three phase squirrel cage induction motor is driven by using the seventeen-level inverter drive proposed in chapter four. A five-level active front-end is realized by the converter topology proposed in chapter two. The converter is run and the performance of the drive is studied at various modulation indices and speeds of the motor. Various aspects like re-generation operation, acceleration and other aspects of the drive have been studied experimentally and the results are presented in detail. For experimental setup, Semikron SKM75GB12T4 IGBT modules have been used to realize the power topology. These IGBTs are driven by M56972L drivers. The control circuit is realized using TMS320F2812 DSP along with Xilinx Spartan 3 FPGA (XC3S200) has been used. The voltages and currents are sensed using LEM LV-20P and LA 55-P hall effect based sensors.

For medium and high-voltage drive applications, multilevel inverters are very popular. It is due to their superior performance compared to 2-level inverters such as reduced harmonic content in the output voltage and current, lower common mode voltage and dv=dt, and lesser voltage stress on power switches. The popular circuit topologies for multilevel inverters are neutral point clamped, cascaded H-bridge and flying capacitor based circuits. There exist different combinations of these basic topologies to realize multilevel inverters with modularity, better fault tolerance, and reliability. Due to these advantages, multilevel converters are getting good acceptance from the industry, and researchers all over the world are continuously trying to improve the performance of these converters. To meet such demands, three multilevel inverter topologies are proposed in this thesis. These topologies can be used for high-power induction motor drives, and the concepts presented are also applicable for synchronous motor drives, grid-connected inverters, etc. To get nearly sinusoidal phase current waveforms, the switching frequency of the conventional inverter has to be increased. It will lead to higher switching losses and electromagnetic interference. The problem with lower switching frequency is the intro- duction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching, and it is possible to eliminate these harmonics by dodecagonal switching. Further improvement in the waveform quality is possible by octadecagonal voltage space-vectors. In this case, the complete elimination of 11th and 13th harmonic is possible for the entire modulation range. The concepts of dodecagonal and octadecagonal voltage space-vectors are used in the proposed inverter topologies. The first topology proposed in this thesis consists of cascaded connection of two H-bridge cells. The two cells are fed from unequal DC voltage sources having a ratio of 1 : 0:366, and this inverter can produce six concentric dodecagonal voltage space- vectors. This ratio of voltages can be obtained easily from a combination of star-delta transformers, since 1 : 0:366 = ( p 3 + 1) : 1. The cascaded connection of two H-bridge cells can generate nine asymmetric pole voltage levels, and the combined three-phase inverter can produce 729 voltage space-vectors (9 9 9). From this large number of combinations, only certain voltage space-vectors are selected, which forms dodecagonal pattern. In the case of conventional multilevel inverters, the voltage space-vector diagram consists of equilateral triangles of equal size, but for the proposed inverter, the triangular regions are isosceles and are having different sizes. By properly placing the voltage space-vectors in a sampling period, it is possible to achieve lower switching frequency for the individual cells, with substantial improvement in the harmonic spectrum of the output voltage. During the experimental veri cation, the motor is operated at di erent speeds using open loop v=f control method. The samples taken are always synchronised with the start of the sector to get synchronised PWM. The number of samples per sector is decreased with increase in the fundamental frequency to limit the switching frequency. Even though many topologies are available in literature, the most preferred topology for drives application such as traction drives is the 3-level NPC structure. This implies that the industry is still looking for viable alternatives to construct multilevel inverter topologies based on available power circuits. The second work focuses on the development of a multilevel inverter for variable speed medium-voltage drive application with dodecagonal voltage space-vectors, using lesser number of switches and power sources compared to earlier implementations. It can generate three concentric 12-sided polygonal voltage space-vectors and it is based on commonly available 2-level and 3-level inverters. A simple PWM timing computation method based on the hexagonal space-vector PWM is developed. The sampled values of the three-phase reference voltages are initially converted to the timings of a two-level inverter. These timings are mapped to the dodecagonal timings using a change of basis transformation. The voltage space- vector diagram of the proposed drive consists of sixty isosceles triangular regions, and the dodecagonal timings calculated are converted to the timings of the inner triangles. A searching algorithm is used to identify the triangular region in which the reference vector is located. A front-end recti er that may be easily implemented using standard star-delta transformers is also developed, to provide near-unity power factor. To test the performance of the inverter drive, an open-loop v=f control is used on a three-phase induction motor under no-load condition. The harmonic spectra of the phase voltages were computed in order to analyse the harmonic distortion of the waveforms. The carrier frequency was kept around 1.2 KHz for the entire range of operation. If the switching frequency is decreased, the conventional hexagonal space-vector based switching introduce signifi cant 5th, 7th, 11th and 13th harmonics in the phase currents. Out of these dominant harmonics, the 5th and 7th harmonics can be completely suppressed using dodecagonal voltage space-vector based switching as observed in the first and second work. It is also possible to remove the 11th and the 13th harmonics by using voltage space-vectors with 18 sides. The last topology is based on multilevel octadecagonal (18-sided polygon) voltage space-vectors, and it has better harmonic performance than the previously mentioned topologies. Here, a multilevel inverter system capable of producing three octadecagonal voltage space-vectors is proposed for the fi rst time, along with a simple timing calculation method. The conventional three-level inverters are only required to construct the proposed drive. Four asymmetric power supply voltages with 0:3054Vdc, 0:3473Vdc, 0:2266Vdc and 0:1207Vdc are required for the operation of the drive, and it is the main drawback of the circuit. Generally front-end isolation transformer is essential for high-power drives and these asymmetric voltages can be easily obtained from the multiple windings of the isolation transformer. The total harmonic distortion of the phase current is improved due to the 18-sided voltage space-vector switching. The ratio of the radius of the largest polygon and its inscribing circle is cos10 = 0:985. This ratio in the case of hexagonal voltage space-vector modulation is cos30 = 0:866, which means that the range of the linear modulation for the proposed scheme is signifi cantly higher. The drive is designed for open-end winding induction motors and it has better fault tolerance. It any of the inverter fails, it can be easily bypassed and the drive will be still functional with reduced speed. Open loop v=f control and rotor flux oriented vector control schemes were used during the experimental verifi cation. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the entire range of operation, the carrier was synchronized with the fundamental. For the synchronization, the sampling period is varied dynamically so that the number of samples in a triangular region is fi xed, keeping the switching frequency around 1.2 KHz. The average execution time for the v=f code was found to be 20 S, where as for vector control it took nearly 100 S. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. To convert the triangle number and the timings to IGBT gate drive logic, an FPGA (XC3S200) was used. A constant dead-time of 1.5 S is also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. Hall-effect sensors were used to measure the phase currents and DC bus voltages. An incremental shaft position encoder with 2500 pulse per revolution is also connected to the motor shaft, to measure the angular velocity. 1200 V, 75 A IGBT half-bridge module is used to realize the switches. The concepts were initially simulated and experimentally verifi ed using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control techniques presented shall still remain applicable.