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Like cell to the human body, transistors are the basic building blocks of any electronics circuits. Silicon has been the industries obvious choice for making transistors. Transistors with large size occupy large chip area, consume lots of power and the number of functionalities will be limited due to area constraints. Thus to make the devices smaller, smarter and faster, the transistors are aggressively scaled down in each generation. Moore's law states that the transistors count in any electronic circuits doubles every 18 months. Following this Moore's law, the transistor has already been scaled down to 14 nm. However there are limitations to how much further these transistors can be scaled down. Particularly below 10 nm, these silicon based transistors hit the fundamental limits like loss of gate control, high leakage and various other short channel effects. Thus it is not possible to favor the silicon transistors for future electronics applications. As a result, the research has shifted to new device concepts and device materials alternative to silicon. Carbon is the next abundant element found in the Earth and one of such carbon based nanomaterial is graphene. Graphene when extracted from Graphite, the same material used as the lid in pencil, have a tremendous potential to take future electronics devices to new heights in terms of size, cost and efficiency. Thus after its first experimental discovery of graphene in 2004, graphene has been the leading research area for both academics as well as industries. This dissertation is focused on the analysis and optimization of graphene based circuits for future electronics. The first part of this dissertation considers graphene based transistors for analog/radio frequency (RF) circuits. In this section, a dual gate Graphene Field Effect Transistor (GFET) is considered to build the case study circuits like voltage controlled oscillator (VCO) and low noise amplifier (LNA). The behavioral model of the transistor is modeled in different tools: well accepted EDA (electronic design automation) and a non-EDA based tool i.e. \simscape. This section of the dissertation addresses the application of non-EDA based concepts for the analysis of new device concepts, taking LC-VCO and LNA as a case study circuits. The non-EDA based approach is very handy for a new device material when the concept is not matured and the model files are not readily available from the fab. The results matches very well with that of the EDA tools. The second part of the section considers application of multiswarm optimization (MSO) in an EDA tool to explore the design space for the design of LC-VCO. The VCO provides an oscillation frequency at 2.85 GHz, with phase noise of less than -80 dBc/Hz and power dissipation less than 16 mW. The second part of this dissertation considers graphene nanotube field effect transistors (GNRFET) for the application of digital domain. As a case study, static random access memory (SRAM) hs been design and the results shows a very promising future for GNRFET based SRAM as compared to silicon based transistor SRAM. The power comparison between the two shows that GNRFET based SRAM are 93% more power efficient than the silicon transistor based SRAM at 45 nm. In summary, the dissertation is to expected to aid the state of the art in following ways: 1) A non-EDA based tool has been used to characterize the device and measure the circuit performance. The results well matches to that obtained from the EDA tools. This tool becomes very handy for new device concepts when the simulation needs to be fast and accuracy can be tradeoff with. 2)Since an analog domain lacks well-design design paradigm, as compared to digital domain, this dissertation considers case study circuits to design the circuits and apply optimization. 3) Performance comparison of GNRFET based SRAM to the conventional silicon based SRAM shows that with maturation of the fabrication technology, graphene can be very useful for digital circuits as well.

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works.

The present work is dedicated to the development of high performance integrated circuits for wireless communications, by acting of three different levels: technologies, devices, and circuits. Silicon-on-Insulator (SOI) CMOS technology is used in the frame of this work. Micromachining technologies are also investigated for the fabrication of three-dimensional tunable capacitors. The reliability of micromachined thin-film devices is improved by the coating of silanes in both liquid- and vapor-phases. Since in telecommunication applications, distortion is responsible for the generation of spurious frequency bands, the linearity behavior of different SOI transistors is analyzed. The validity range of the existing low-frequency nonlinear characterization methods is discussed. New simple techniques valid at both low- and high-frequencies, are provided, based on the integral function method and on the Volterra series. Finally, the design of a crucial nonlinear circuit, the voltage-controlled oscillator, is introduced. The describing function formalism is used to evaluate the oscillation amplitude and is embedded in a design methodology. The frequency tuning by SOI varactors is analyzed in both small- and large-signal regimes.

Le travail présenté ici s'inscrit dans la perspective du développement de modules électroniques à très faible coût et à très faible consommation pour les réseaux de capteurs sans fils (WSN). Il traite de la conception et du test d'une chaîne de réception RF compatible avec la norme IEEE 802.15.4 pour la bande ISM 2.4GHz. L'interface RF objet de notre étude inclue toutes les fonctions depuis l'antenne jusqu'au 1er étage du filtre analogique en bande de base, à partir duquel le gain devient suffisant pour masquer le bruit introduit par le reste de la chaîne de réception. Ce mémoire articulé autour de quatre chapitres, décrit toutes les étapes depuis la définition des spécifications de la chaîne de réception jusqu'à la présentation de ses performances, en passant par l'étude de son architecture et la conception de ses différents étages. Suite à l'étude de l'impact des interféreurs IEEE 802.15.4 et IEEE 802.11b présents dans la bande ISM 2.4GHz, une architecture utilisant une fréquence intermédiaire de 6MHz a été retenue. En outre, pour pouvoir répondre aux spécifications fixées, cette architecture est composée de plusieurs étages innovants ou originaux tels qu'un balun intégré trois accès, un amplificateur faible bruit sans inductance, un mélangeur passif piloté par un signal local (OL) à très faible rapport cyclique ainsi qu'un filtre bande de base optimisé en bruit et en linéarité. Intégré dans une technologie CMOS 90nm, ce récepteur occupe une surface de 0.07mm², ou 0.23mm² en incluant le balun intégré, qui représente une réduction de 70% par rapport à l'état de l'art des puces compatibles avec le standard IEEE 802.15.4. En prenant en compte la consommation dynamique de toute la chaîne de mise en forme du signal OL, la tête de réception précédemment décrite consomme seulement 4mA sous une tension d'alimentation de 1.35V. Enfin, en incluant le balun intégré, le gain est de 35dBv/dBm, le facteur de bruit de 7.5dB, l'IIP3 de -10dBm et la réjection d'image supérie ure à 32dB. Ces performances placent ce récepteur parmi les récepteurs RF les plus performants pour cette application. Les nombreux principes mis en Suvre sont par ailleurs transposables à d'autres bandes de fréquences et à d'autres standards de communication.

LOW power operation for wireless radio receivers has been gaining importance lately on account of the recent spurt of growth in the usage of ubiquitous embedded mobile devices. These devices are becoming relevant in all domains of human influence. In most cases battery life for these devices continue to be an us-age bottleneck as energy storage techniques have not kept pace with the growing demand of such mobile computing devices. Many applications of these radios have limitations on recharge cycle, i.e. the radio needs to last out of a battery for long duration. This will specially be true for sensor network applications and for im-plantable medical devices. The search for low power wireless receivers has become quite advanced with a plethora of techniques, ranging from circuit to architecture to system level approaches being formulated as part of standard design procedures. However the next level of optimization towards “Smart” receiver systems has been gaining credence and may prove to be the next challenge in receiver design and de-velopment. We aim to proceed further on this journey by proposing Power Scalable Wireless Receivers (PSRX) which have the capability to respond to instantaneous performance requirements to lower power even further. Traditionally low power receivers were designed for worst-case input conditions, namely low signal and high interference, leading to large dynamic range of operation which directly im-pacts the power consumption. We propose to take into account the variation in performance required out of the receiver, under varying Signal and Interference conditions, to trade-off power. We have analyzed, designed and implemented a Power Scalable Receiver tar-geted towards low data-rate receivers which can work for Zigbee or Bluetooth Low Energy (BLE) type standards. Each block of such a receiver system was evaluated for performance-power trade-offs leading to identification of tuning/control knobs at the circuit architecture level of the receiver blocks. Then we developed an usage algorithm for finding power optimal operational settings for the tuning knobs, while guaranteeing receiver reception performance in terms of Bit-Error-Rate (BER). We have proposed and demonstrated a novel signal measurement system to gen-erate digitized estimates of signal and interference strength in the received signal, called Received Signal Quality Indicator (RSQI). We achieve a RSQI average energy consumption of 8.1nJ with a peak energy consumption of 9.4nJ which is quite low compared to the packet reception energy consumption for low power receivers, and will be substantially lower than the energy savings which will be achieved from a power scalable receiver employing a RSQI. The full PSRX system was fabricated in UMC 130nm RF-CMOS process to test out our concepts and to formally quantify the power savings achieved by following the design methodology. The test chip occupied an area of 2.7mm2 with a peak power consumption of 5.5mW for the receiver chain and 18mW for the complete PSRX. We were able to meet the receiver performance requirements for Zigbee standard and achieved about 5X power savings for the range of input condition variations.

Cette thèse présente un système bioélectronique prometteur, l’Hynet. Ce Réseau Hybride (vivant-artificiel) est conçu pour l’étude du comportement à long terme des cellules électrogénératrices, comme les neurones et les cellules betas, en deux aspects : l’individuel et en réseau. Il est basé sur une boucle fermée et sur la communication en temps réel entre la culture cellulaire et une unité artificielle (Matériel, Logiciel). Le premier Hynet utilise des Matrices d’électrodes (MEA) commerciales qui limitent les performances spatiotemporelles du Hynet. Une nouvelle Matrice d’électrodes intelligente (iMEA) est développée. Ce nouveau circuit intégré, analogique et mixte, fournit une interface à forte densité, à forte échelle et adaptative avec la culture. Le nouveau système améliore le traitement des données en temps réel et une acquisition faible bruit du signal extracellulaire. / This thesis presents a promising new bioelectronics system, the Hynet. The Hynet is a Hybrid (living-artificial) Network, developed to study the long-term behavior of electrogenic cells (such as Neurons or Beta-cells), both individually and in a network. It is based on real-time closed-loop communication between a cell culture (bioware) and an artificial processing unit (hardware and software). In the first version of our Hynet, we use commercial Multielectrode Arrays (MEA) that limits its spatiotemporal performances. A new Intelligent Multielectrode Array (iMEA) is therefore developed. This new analog/mixed integrated circuit provides a large-scale, high-density, and adaptive interface with the Bioware, which improves the real-time data processing and the low-noise acquisition of the extracellular signal. / Esta dissertação de doutorado apresenta um sistema bioeletrônico auspicioso, o Hynet. Esta Rede Híbrida (viva e artificial), é concebida para o estudo do comportamento à longo prazo de células eletrogeneradoras (como neurônios ou células beta), em dois aspectos : individual e em redes. Ele é baseado na comunicação bidirecional, em laço fechado e em tempo real entre uma cultura celular (Bioware) e uma unidade artificial (Hardware ou Software). Um primeiro Hynet é apresentado, mas o uso de Matrizes de Eletrodos (MEA) comerciais limita a performance do sistema. Finalmente, uma nova Matriz de Eletrodos Inteligente (iMEA) é desenvolvida. Este novo circuito integrado fornece uma interface adaptativa, em alta densidade e grande escala, com o Bioware. O novo sistema melhora o processamento de dados em tempo real e a aquisição baixo ruído do sinal extracelular.

Thesis submitted in fulfillment of the requirements for the degree Master of Technology:Electrical Engineering in the Faculty ofEngineering at the Cape Peninsula University of Technology Supervisor:Prof MTE KAHN Bellville December 2013 / The work presented in this thesis consists of the simulation of a cooling plant for a future mobile satellite ground station in order to minimize the effects of the thermal noise and to maintain comfort temperatures onboard the same station. Thermal problems encountered in mobile satellite ground stations are a source of poor quality signals and also of the premature destruction of the front end microwave amplifiers. In addition, they cause extreme discomfort to the mission operators aboard the mobile station especially in hot seasons. The main concerns of effective satellite system are the quality of the received signal and the lifespan of the front end low noise amplifier (LNA). Although the quality of the signal is affected by different sources of noise observed at various stages of a telecommunication system, thermal noise resulting from thermal agitation of electrons generated within the LNA is the predominant type. This thermal noise is the one that affects the sensitivity of the LNA and can lead to its destruction. Research indicated that this thermal noise can be minimized by using a suitable cooling system. A moveable truck was proposed as the equipment vehicle for a mobile ground station. In the process of the cooling system development, a detailed quantitative study on the effects of thermal noise on the LNA was conducted. To cool the LNA and the truck, a 2 kW solar electric vapor compression system was found the best for its compliance to the IEA standards: clean, human and environment friendly. The principal difficulty in the development of the cooling system was to design a photovoltaic topology that would ensure the solar panels were always exposed to the sun, regardless the situation of the truck. Simulation result suggested that a 3.3 kW three sided pyramid photovoltaic topology would be the most effective to supply the power to the cooling system. A battery system rated 48 V, 41.6 Ah was suggested to be charged by the PV system and then supply the power to the vapor compression system. The project was a success as the objective of this project has been met and the research questions were answered.

This thesis deals with the theoretical description of the qualitative characteristics and parameters of some modern active elements, also discusses the theory of signal flow graphs at the level applicable for the following frequency filter design methods. The thesis is also generally discussed the issue with the circuit simulator PSpice modeling theory and voltage amplifiers on the basic 6-levels. The practical part of the work is divided into two parts. The first practical part is dedicated to design four levels of simulation model of components LNVGA element. The second practical part contains detailed theoretical proposals for three circuit structures implementing the frequency filters 2nd order (based on the basic structure of the OTA-C) using signal flow graphs with configuration options of Q and fm based on the parameters of active elements in the peripheral structure and their verification with prepared LNVGA model layers.

A 5 GHz continuous unlicensed bandwidth is available at millimeter-wave (mm-wave) frequencies around 60 GHz and offers the prospect for multi gigabit wireless applications. The inherent atmospheric attenuation at 60 GHz due to oxygen absorption makes the frequency range ideal for short distance communication networks. For these mm-wave wireless networks, the low noise amplifier (LNA) is a critical subsystem determining the receiver performance i.e., the noise figure (NF) and receiver sensitivity. It however proves challenging to realise high performance mm-wave LNAs in a silicon (Si) complementary metal-oxide semiconductor (CMOS) technology. The mm-wave passive devices, specifically on-chip inductors, experience high propagation loss due to the conductivity of the Si substrate at mm-wave frequencies, degrading the performance of the LNA and subsequently the performance of the receiver architecture. The research is aimed at realising a high performance mm-wave LNA in a Si BiCMOS technology. The focal points are firstly, the fundamental understanding of the various forms of losses passive inductors experience and the techniques to address these issues, and secondly, whether the performance of mm-wave passive inductors can be improved by means of geometry optimising. An associated hypothesis is formulated, where the research outcome results in a preferred passive inductor and formulates an optimised passive inductor for mm-wave applications. The performance of the mm-wave inductor is evaluated using the quality factor (Q-factor) as a figure of merit. An increased inductor Q-factor translates to improved LNA input and output matching performance and contributes to the lowering of the LNA NF. The passive inductors are designed and simulated in a 2.5D electromagnetic (EM) simulator. The electrical characteristics of the passive structures are exported to a SPICE netlist which is included in a circuit simulator to evaluate and investigate the LNA performance. Two LNAs are designed and prototyped using the 13μ-m SiGe BiCMOS process from IBM as part of the experimental process to validate the hypothesis. One LNA implements the preferred inductor structures as a benchmark, while the second LNA, identical to the first, replaces one inductor with the optimised inductor. Experimental verification allows complete characterization of the passive inductors and the performance of the LNAs to prove the hypothesis. According to the author's knowledge, the slow-wave coplanar waveguide (S-CPW) achieves a higher Q-factor than microstrip and coplanar waveguide (CPW) transmission lines at mm-wave frequencies implemented for the 130 nm SiGe BiCMOS technology node. In literature, specific S-CPW transmission line geometry parameters have previously been investigated, but this work optimises the signal-to-ground spacing of the S-CPW transmission lines without changing the characteristic impedance of the lines. Optimising the S-CPW transmission line for 60 GHz increases the Q-factor from 38 to 50 in simulation, a 32 % improvement, and from 8 to 10 in measurements. Furthermore, replacing only one inductor in the output matching network of the LNA with the higher Q-factor inductor, improves the input and output matching performance of the LNA, resulting in a 5 dB input and output reflection coefficient improvement. Although a 5 dB improvement in matching performance is obtained, the resultant noise and gain performance show no significant improvement. The single stage LNAs achieve a simulated gain and NF of 13 dB and 5.3 dB respectively, and dissipate 6 mW from the 1.5 V supply. The LNA focused to attain high gain and a low NF, trading off linearity and as a result obtained poor 1 dB compression of -21.7 dBm. The LNA results are not state of the art but are comparable to SiGe BiCMOS LNAs presented in literature, achieving similar gain, NF and power dissipation figures. / Dissertation (MEng)--University of Pretoria, 2012. / Electrical, Electronic and Computer Engineering / unrestricted