For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked. Cooling and power delivery are among these key challenges in the integration of high performance 3D ICs. To address these challenges, microchannel heat sinks for inter-stratum cooling and through-silicon vias (TSVs) for signaling and power delivery between stacked ICs were explored. Novel integration schemes to integrate these uidic and electrical interconnects in conventional CMOS processes were also explored. Compact physical modeling was utilized to understand the trade-offs involved in the integration of electrical and microfluidic interconnects in a 3D IC stack. These concepts were demonstrated experimentally by showing different CMOS compatible methods of fabricating microchannels and integration of high aspect ratio (~20:1) and high density (200,000/cm²) electrical TSVs in the fins of the microchannels for signaling and power delivery. A novel mesh process for bottom up plating of high aspect ratio TSVs is also shown in this work. Fluidic reliability measurements are shown to demonstrate the feasibility of this technology. This work also demonstrates the design and fabrication of a 3D testbed which consists of a 2 chip stack with microchannel cooling on each level. Preliminary testing of the stack along with interlayer electro-fluidic I/Os has also been demonstrated.

As the convergence of multiple functions in a single electronic device drives current electronic trends, the need for increasing integration density is becoming more emphasized than in the past. To keep up with the industrial need and realize the new system integration law, three-dimensional (3-D) integration called System-on-Package (SoP) is becoming necessary. However, the commercialization of 3-D integration should overcome several technical barriers, one of which is the difficulty for the electrical design of interconnections. The 3-D interconnection design is difficult because of the modeling challenge of electrical coupling from the complicated structures of a large number of interconnections. In addition, mixed-signal design requires broadband modeling, which covers a large frequency spectrum for integrated microsystems. By using currently available methods, the electrical modeling of 3-D interconnections can be a very challenging task. This dissertation proposes a new method for constructing a broadband model of a large number of 3-D interconnections. The basic idea to address the many interconnections is using modal basis functions that capture electrical effects in interconnections. Since the use of global modal basis functions alleviates the need for discretization process of the interconnection structure, the computational cost is reduced considerably. The resultant interconnection model is a RLGC model that describes the broadband electrical behavior including losses and couplings. The smaller number of basis functions makes the interconnection model simpler, and therefore allows the generation of network parameters at reduced computational cost. Focusing on the modeling of bonding wires in stacked ICs and through-silicon via (TSV) interconnections, this research validates the interconnection modeling approach using several examples from 3-D full-wave EM simulation results.

Laser Induced Forward Transfer (LIFT) techniques show promise as a disruptive technology which will enable the placement of components smaller than what conventional pick-and-place techniques are capable of today. Limitations of current die-attach techniques are presented and discussed and present the opportunity for a new placement method. This study introduces the Thermo-Mechanical Selective Laser Assisted Die Transfer (tmSLADT) process and is an application of the unique blistering behavior of a dynamic releasing layer when irradiated by low energy focused UV laser pulses. The potential of tmSLADT as the next generation LIFT technique is demonstrated by the "touchless" transfer of 65 μm thick silicon tiles between two substrates spaced 195 μm apart. Additionally, the advantages of an enclosed blister-actuator mechanism over previously studied ablative and thermal releasing techniques are discussed. Finally, experimental results studying transfer precision indicate this non optimized die transfer process compares with, and may exceed, the placement precision of current assembly techniques. / Defense Microelectronics Activity (DMEA) under agreement number H94003-09-2-0905

Les composants dédiés et actuellement disponibles pour le marché automobileprésentent une grande diversité technologique tant au niveau puce que stratégie de packaging ouencore architecture module (mono-puce ou multi-puce) pour des performances équivalentes. Cetteétude s’est attachée à développer une méthodologie d’évaluation de la fiabilité de deux filièrestechnologiques particulières de modules de LEDs multi-puce : l’une intègre une technologie verticale(VTF pour Vertical Thin Film) tandis que la seconde est focalisée sur une structure par puce montéeretournée(TFFC pour Thin Film Flip Chip). La méthodologie s’articule autour de trois principaux axes:· La connaissance des structures et le développement de modèles électro-optiques et thermiquesmulti-puce permettant d’extraire les paramètres clés à suivre au travers d’un panel varié detechniques d’analyse physique et non-destructives incluant les aspects électriques, optiques,thermiques….· Une analyse comportementale de robustesse par paliers afin de dégager les margesopérationnelles de fonctionnement ainsi que les modes et les signatures caractéristiques dedéfaillance.· Une étude de fiabilité conduite à partir de différents régimes de contraintes accélérées pourestimer les durées de vie moyennes de ces nouveaux composants en environnement automobileet l’impact au niveau système.Les résultats mettent en évidence une durée de vie très dépendante de la filière technologique(facteur 6 entre les deux filières étudiées). Les analyses de défaillance ont permis d’identifierprécisément les comportements de ces nouvelles sources d’éclairage pour dégager des indicateursprécoces de défaillance. Enfin, des préconisations ont été extraites afin de fiabiliser les futursprojecteurs à sources LEDs de puissance pour les applications en automobile. / With rapid development of Lighting Emitting Diode (LED) market, LED performancesare now suitable for automotive high beam / low beam lighting applications. Due to the need of UltraHigh Brightness (UHB-LEDs), LEDs are packaged on high thermal conductivity materials to obtainmultichip module (4 chips in series), which deliver up to 1000 lumens at 1A. Currently, several LEDtechnologies are commercially offered for the same performances, and different packaging strategieshave been implemented in terms of chip configuration, bonding, down conversion phosphor layerand mechanical protection to optimize performances. This study addresses a dedicated methodologyfor reliability analysis, applied on two LED chip packaging technologies: On the one hand, a VerticalThin Film (VTF) technology; on the other hand a Thin Film Flip Chip (TFFC). Our methodology is basedon 3 main items: Packaging technology structure, materials analysis and electro-optical and thermal multichipmodels for both technologies to understand and extract the key parameters to monitor duringageing tests. Robustness assessment tests to define operating margins, adjust accelerated life-testingconditions, and identify failures signatures. Reliability study through a 6 000 hours High Temperature Operating Life (HTOL) acceleratedtests, to predict the Mean Time To Failure (MTTF) of these new light source technologiesregarding the automotive mission profile. Linked to failure analysis, convincing failuremechanisms are proposed.Based on these results, parametric variations are compared to failure analysis results topropose failure mechanisms. The HTOL tests reveal that both LED technologies have their specificreliability behavior and failure modes: catastrophic failure and gradual failure. Predictive lifetimeestimations (L70B50) of these multichip modules give a factor 6 between both technologies.Beyond these reliability results, the multichip architecture brings new issues for Solid StateLighting (SSL) sources in automotive, as well as partial failure or unbalanced behavior after stress.These new issues are discussed through the behavior modeling of a 10 LED modules batch for bothfailure modes. Modeling results demonstrate that the predictive lifetime of a LED multichiparchitecture is directly related with the LED technology failure mode.

This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. In this dissertation, a fine-pitch ball-grid array (FBGA) package, a multichip module (MCM)-L package, and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared to those of inductors monolithically integrated on Si and GaAs substrates. All the inductors are modeled with a physical, simple, equivalent two-port model for the VCO design as well as for phase noise analysis. The losses in an LC-tank are analyzed from the phase noise perspective. For the implementation of VCOs, the effects of the interconnection between the embedded inductor and the VCO circuit are investigated. The VCO using the on-chip inductors is designed as a reference. The performance of VCOs using the embedded inductor in a FBGA and a WLP is compared with that of a VCO using the on-chip inductor. The VCO design is optimized from the high-Q perspective to enhance performance. Through this optimization, less phase noise, lower power consumption, and a wider frequency tuning range are obtained simultaneously.

Wireless communications have been an indispensable aspect of everyday life, and there is an increasing consumer demand for accessing several wireless communication technologies from a single, compact, mobile device. System-on-package (SOP) technology is an advanced packaging technology that has been proven to realize the convergence of multiple functions into miniaturized, high-performance systems to meet this demand. With the advancements in the SOP technology, the miniaturization of the front-end module has been achieved using embedded passives in multilayer packages. However, the integration of the antenna directly on the module package is still the barrier to achieve a fully-integrated, high-performance RF SOP system. The main reason for this missing link is that integrating the antenna on the package requires miniaturizing the antenna, which is a difficult task. The focus of this dissertation is to design high-performance antennas along with developing techniques for miniaturization and system-on-package (SOP) integration of these antennas to achieve fully-integrated SOP systems using advanced multilayer organic substrates and thin-film magneto-dielectric materials. The targeted spectrum for the antenna designs are 2.4/5 GHz WLAN/WiMAX and 60 GHz WPAN bands. Several novel antenna designs and configurations to integrate the antenna on the package along with the module are discussed in this dissertation. The advanced polymers used in this research are Liquid Crystalline Polymer (LCP), RXP, and thin-film magneto-dielectrics.