High-level radioactive waste (HLW) poses threat to the biosphere. Geological disposal is accepted as a safe way for HLW disposal. Waste canisters made of Sintered Silicon Carbide (SSiC) are proposed and geomechanical safety aspects relating to such SSiC canisters are investigated. First part of the thesis reviews the state-of-the-art and demands for HLW disposal. The reason for considering Silicon Carbide (SiC) as canister material is explained. Especially in terms of corrosion and lifetime, ceramics and especially SiC is superior to metals or concrete. The only concern is its brittle behavior. The second part of the thesis presents results on static and dynamic mechanical properties of SiC in general and in particular for SSiC based on literature review and own lab tests. Although strength values for SiC and especially SSiC are very high, the extreme brittle behavior has to be considered in case of impact or point-like loading. The third and most extensive part of the thesis part contains numerical simulations, which consider most critical potential loading situations during transport and installation of the canisters underground. Both, pure elastic continuum and DEM based models are used considering the following loading situations (critical scenarios): Freefall of canister during transport or installation (FF), Impact by falling rock block at disposal site (RF), Point loading due to accidental insertion of small stone below the canister (PL), Anisotropic earth pressure loading after disposal (EP). Coating to protect the canisters against damage is investigated and preliminary parameters in terms of stiffness and thickness are recommended.

SiC in Space is one of the experiments on KTH’s miniature satellite, MIST. The experiment carries out tests on bipolar junction transistors of silicon and silicon carbide. This thesis describes how the characteristics of a transistor can be measured using analog circuits. The presented circuit design will work as a prototype for the SiC in Space experiment. The prototype measures the base current, the collector current, the base-emitter voltage as well as the temperature of the transistor. This thesis describes how a test circuit may be designed. The selected design has been constructed in incremental steps, with each design choice explained. Different designs have been developed. The designs have been verified with simulations. We have also constructed and tested three different prototypes on breadboards and printed circuit boards. / SiC in Space är ett av experimenten på KTHs miniatyrsatellit, MIST. Experimentet utför test på bipolära transistorer av kisel och kiselkarbid. Detta examensarbete förklarar hur transistorns karakteristik kan mätas med analoga kretsar. Den framtagna kretsdesignen kommer att fungera som en prototyp till SiC in Space-experimentet. Prototypen mäter basströmmen, kollektorströmmen, bas-emitter-spänningen samt temperaturen för transistorn. Detta examensarbete förklarar hur en testkrets kan designas. Den valda designen byggs i inkrementella steg, där varje designval förklaras. Olika designer har utvecklats. Designerna har verifierats genom simuleringar. Vi har också konstruerat och testat tre olika prototyper på kopplingsdäck och kretskort.

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Die vorliegende Arbeit behandelt die Charakterisierung von epitaktischem Graphen auf Siliziumkarbid (0001) mittels Raman-Spektroskopie. Nach der Einführung theoretischer sowie experimenteller Grundlagen werden das Wachstum von Graphen auf Siliziumkarbid (SiC) behandelt und die untersuchten Materialsysteme vorgestellt. Es wird gezeigt, dass das Raman-Spektrum von epitaktischem Graphen auf SiC (0001) neben den Phononenmoden des Graphens und des Substrats weitere Signale beinhaltet, welche der intrinsischen Grenzflächenschicht, dem Buffer-Layer, zwischen Graphen und SiC zugeordnet werden können. Das Raman-Spektrum dieser Grenzflächenschicht kann als Abbild der phononischen Zustandsdichte interpretiert werden. Fortführend werden verspannungsinduzierte Änderungen der Phononenenergien der G- und 2D-Linie im Raman-Spektrum von Graphen untersucht. Dabei werden starke Variationen des Verspannungszustands beobachtet, welche mit der Topographie der SiC-Oberfläche korreliert werden können und erlauben, Rückschlüsse auf Wachstumsmechanismen zu ziehen. Die Entwicklung einer neuen Messmethode, bei der das Raman-Spektrum von Graphen durch das SiC-Substrat aufgenommen wird, ermöglicht die detektierte Raman-Intensität um über eine Größenordnung zu erhöhen. Damit wird die Raman-spektroskopische Charakterisierung eines Graphen-Feldeffekttransistors mit top gate ermöglicht und ein umfassendes Bild des Einflusses der Ladungsträgerkonzentration und der Verspannung auf die Positionen der G- und 2D-Raman-Linien von quasifreistehendem Graphen auf SiC erarbeitet.

<p>This dissertation presents research work related to laser micro sintering, laser micro machining and laser-induced plasma. Firstly, we present extensive experimental studies of double-pulse laser micro sintering (DP-LMS), which typically utilizes the high pressure generated by laser-induced plasma over the powder bed surface to promote molten flow and enhance densification. Chapter 2 shows a single-track experimental study of the DP-LMS process using cobalt powder. The related fundamental mechanisms and effects of different laser parameters on the sintering results are analyzed with the help of <em>in-situ</em> time-resolved temperature measurements. Chapter 3 shows a multi-track experimental study of the DP-LMS process using iron powder. The sintered materials are characterized via the top surface porosity, elemental composition, grain microstructure, nanohardness and metal phase. Three strategic guidelines for laser parameter selection are summarized in the end. Chapter 4 shows time-resolved imaging and OES measurements for plasma induced during DP-LMS. The plasma temperature and free electron number density are deduced by its optical emission spectra (OES). These three chapters have clearly demonstrated DP-LMS can produce much more continuous and densified materials than LMS only using the sintering or pressing laser pulses.</p> <p><br></p> <p>Then, we present laser micro grooving of silicon carbide (SiC) in Chapter 5 by ultrasound-assisted water-confined laser micromachining (UWLM), in comparison with laser machining in water without ultrasound and laser machining in air. UWLM applies <em>in-situ</em> ultrasound to the water-immersed workpiece surface to improve the machining quality and/or productivity. Time-resolved water pressure measurements are carried out to help analyze relevant mechanisms. It has been demonstrated UWLM can be a competitive approach to produce high-quality micro grooves on SiC. The crack problem appears to be effectively solved using a high pulse repetition rate.</p> <p><br></p> <p>Finally, we report a double-front phenomenon for plasma induced by high-intensity nanosecond laser ablation of aluminum in Chapter 6. An additional plasma front is observed via an intensified CCD (ICCD) camera, which propagates very fast at the beginning but stops propagating soon after the laser pulse mostly ends. Its formation could be caused by the inverse bremsstrahlung absorption of laser energy by the ionized ambient gas. Three possible mechanisms on how the ambient gas breakdown is initiated are proposed. </p>

Advances in wide-bandgap semiconductor devices have increased the allowable operating temperature of power electronic systems. High-temperature devices can benefit applications such as renewable energy, electric vehicles, and space-based power electronics that currently require bulky cooling systems for silicon power devices. Cooling systems can typically be reduced in size or removed by adopting wide-bandgap semiconductor devices, such as silicon carbide. However, to do this, semiconductor device packaging with high reliability at high temperatures is necessary. Transient liquid phase (TLP) die-attach has shown in literature to be a promising bonding technique for this packaging need. In this work TLP has been comprehensively investigated and characterized to assess its viability for high-temperature power electronics applications. The reliability and durability of TLP die-attach was extensively investigated utilizing electrical resistivity measurement as an indicator of material diffusion in gold-indium TLP samples. Criteria of ensuring diffusive stability were also developed. Samples were fabricated by material deposition on glass substrates with variant Au–In compositions but identical barrier layers. They were stressed with thermal cycling to simulate their operating conditions then characterized and compared. Excess indium content in the die-attach was shown to have poor reliability due to material diffusion through barrier layers while samples containing suitable indium content proved reliable throughout the thermal cycling process. This was confirmed by electrical resistivity measurement, EDS, FIB, and SEM characterization. Thermal and mechanical characterization of TLP die-attached samples was also performed to gain a newfound understanding of the relationship between TLP design parameters and die-attach properties. Samples with a SiC diode chip TLP bonded to a copper metalized silicon nitride iv substrate were made using several different values of fabrication parameters such as gold and indium thickness, Au–In ratio, and bonding pressure. The TLP bonds were then characterized for die-attach voiding, shear strength, and thermal impedance. It was found that TLP die-attach offers high average shear force strength of 22.0 kgf and a low average thermal impedance of 0.35 K/W from the device junction to the substrate. The influence of various fabrication parameters on the bond characteristics were also compared, providing information necessary for implementing TLP die-attach into power electronic modules for high-temperature applications. The outcome of the investigation on TLP bonding techniques was incorporated into a new power module design utilizing TLP bonding. A full half-bridge inverter power module for low-power space applications has been designed and analyzed with extensive finite element thermomechanical modeling. In summary, TLP die-attach has investigated to confirm its reliability and to understand how to design effective TLP bonds, this information has been used to design a new high-temperature power electronic module.

Wide bandgap (WBG) semiconductor devices are becoming increasing popular in power electronics applications. However, WBG semiconductor devices generate a substantial amount of conducted electromagnetic interference (EMI) compared to silicon (Si) devices due to their ability to operate at higher switching frequencies, higher operating voltages and faster slew rates. This thesis explores and analyzes EMI mitigation techniques that can be applied to a power module architecture at the packaging level. In this thesis, the EMI footprint of four different module architectures is measured experimentally. A time domain LTspice simulation model of the experimental test setup is then built. The common mode (CM) EMI emissions that escape the baseplate of the module into the converter is then examined through the simulation. The simulation is used to explore the CM noise footprint of eight additional module architectures that were found in literature. The EMI trends and the underlying mitigation principle for the twelve modules is explained by highlighting key differences in the architectures using common mode equivalent modelling and substitution and superposition theorem. The work aims to help future module designers by not only comparing the EMI performance of the majority of module architectures available in literature but by also providing an analysis methodology that can be used to understand the EMI behavior of any new module architecture that has not been discussed. Although silicon carbide (SiC) modules are used for this study, the results are applicable for any WBG device. / M.S. / As society moves towards the electric grid of the future, there have been increasing calls for high efficiency, high power density, and low electromagnetic interference (EMI) power electronic converters. EMI is a big problem when using wide-bandgap (WBG) devices as these devices can switch very quickly and handle higher voltages when compared to silicon devices. In this study, ways to reduce EMI in a WBG power module through twelve different types of packaging are explored. Four WBG power modules are designed and fabricated in the lab, whereas a simulation model was created to study the EMI behavior of the remaining eight power module. The EMI behavior of these modules is explained using common mode (CM) equivalent modeling and substitution and superposition theorem. This study is important because WBG devices are becoming more and more popular in power electronic applications. The author hopes the findings and analysis presented in this paper can help future module designers reduce the EMI footprint of modules they design.

The thesis focuses on designing and characterizing SiC 3.3 kV Diffused Metal-Oxide Semiconductor Field-Effect Transistor (DMOSFET)s with a Ron that is significantly lower than that of current commercial devices. The On-state resistance and breakdown voltage are then adjusted by adding a Super-Junction structure. Because of the pillar structure below the p-base area, the depletion will occur both vertically and horizontally and keeps the electric field distribution throughout the drift layer constant. The Super Junction Metal-Oxide Semiconductor Field-Effect Transistor (SJ MOSFET) has a good advantage compared to DMOSFETs. Due to its capacity to tolerate higher breakdown voltages and the fact that it does not require an increase in cell pitch to reach higher voltages, the Super-Junction approach is now the subject of effective research as compared to IGBTs and DMOSFETs. Silicon Carbide , a material with a wide bandgap that facilitates high temperature operation, high blocking voltage, high current flow and high switching frequency, is used to construct the device. In order to maintain a consistent electric field throughout the device, the concentration of the n and p pillars was chosen with a good charge balance between them. The outcomes of designing and simulating a DMOSFET, a Semi-SJ MOSFET, and a Full SJ MOSFET are compared in this research. The semi SJ device resulted in a Ron of 18.4 mΩcm2 and a Vb of 4.1 kV. The full SJ device reached a Ron of 12.4 mΩcm2 and a breakdown voltage of 4.2 kV. One optimized device was chosen from the semi SJ devices and used in several TCAD simulations, and the outcomes were evaluated based on the JFET width, pillar thickness, and charge imbalance between the p and n pillars. In this study, the device was also modelled for 6.5 kV and 10 kV SiC blocking voltage capabilities; the findings are also discussed. / Denna uppsats fokuserar på att utveckla och karakterisera 3.3 kV kiselkarbidbaserade DMOSFET-transistorer med betydligt lägre framspänningsfall jämfört med kommersiella halvledarkomponenter. Framspänningsfallet och spärrspänningen modifieras genom att använda en pelarliknande halvledarstruktur i drift regionen, dvs. en super-junction [SJ] struktur. På grund av pelarstrukturen under p-bas området, uppträder utarmningsområdet av laddningsbärare både vertikalt och horisontellt och ger ett konstant elektriskt fält genom drift-regionen. Super-junction transistorer har flera fördelar jämfört med komponenter i DMOSFET struktur. På grund av sin kapacitet att motstå högre spärrspänningar och genom att strukturen inte behöver en större enhetscellbredd för att nå högre spärrspänning, så är just nu super-junction strukturer i stort forskningsfokus jämfört med IGBT och DMOSFET komponenter. Kiselkarbid, ett material med ett brett bandgap, möjliggör komponenter för höga temperaturer, höga spärrspänningar, höga elektriska strömmar, samt höga växlingsfrekvenser, har använts för att bygga de undersökta komponenterna. För att generera ett konstant elektriskt fält över drift-regionen, så har dopningsnivåerna för n- och p- pelarna valts för att hålla en bra laddningsbalans mellan dem. Simuleringsresultaten av dessa komponentstrukturer, DMOSFET, halv-SJ MOSFET, och hel-SJ MOSFET är jämförda i detta projekt. Halv-SJ MOSFET transistorn resulterade i ett framspänningsfall på 18.4 mΩcm2 och når en spärrspänning av 4.1 kV. Hel-SJ MOSFET strukturen uppnår ett framspänningsfall på 12.4 mΩcm2 och med spärrspänning av 4.2 kV. En optimerad halv-SJ struktur valdes ut för att genomföra ytterligare TCAD simuleringsstudier om effekterna av JFET bredd, pelartjocklek, samt laddningsobalans mellan n- och p- pelarna. I den här studien simulerades även komponentstrukturer för 6.5 kV och 10 kV spärrspänningsklasser; även dessa resultat diskuteras i rapporten.

Silicon Carbide as a wide-bandgap semiconductor has several physical and electrical advantages over Silicon for high voltage and high frequency applications. SiC as a MOSFET device has a lot of great characteristics like lower on-resistance and low input capacitances. However, due to its high switching capabilities, SiC MOSFET-based converter circuits experience higher dv/dt and di/dt transients and are therefore more susceptible to parasitic elements. This thesis investigates the interaction of the parasitic gate inductance and resistance on the switching behaviour of SiC DMOSFET (planar) and UMOSFET (trench). To examine this, a double pulse test (DPT) setup was utilised both in simulation and experimentally. The influence of the gate inductance and resistance on the oscillation behaviour in the VGS during the miller period was found to be dependent on the condition of the upper device. Furthermore, the upper device was discovered to have a high impact on the oscillations in the VGS via its source inductance. The gate inductance showed a mixed impact on IDS and VDS overshoot, with IDS overshoot reducing with increasing gate inductance and the reverse case for VDS. The gate resistance, however, showed a consistent impact on both IDS and VDS overshoot, with both reducing with increasing gate resistance. These results ultimately point to the impact of di/dt and dv/dt transients. An interesting result observed on these root causes showed that in the DPT arrangement used, lower test current levels may have a more significant impact on the oscillations in the VGS than higher test current when varying the test currents, with 20 A having the highest impact on the oscillations in simulations and 15 A having the highest impact in experimental verification. On the switching energy, the gate inductance was not shown to have a significant impact on switching losses while the gate resistance had a much more significant impact on the switching losses. / Kiselkarbid som halvledare med brett bandgap har flera fysiska och elektriska fördelar jämfört med kisel för högspännings- och högfrekvensapplikationer. SiC som en MOSFET-enhet har många fantastiska egenskaper som lägre resistans och låga ingångskapacitanser. Men på grund av dess höga omkopplingsförmåga upplever SiC MOSFET-baserade omvandlarkretsar högre dv/dt och di/dt transienter och är därför mer mottagliga för parasitiska element. Denna avhandling undersöker interaktionen mellan gate-drivkretsens parasitära induktans och resistans på kopplingsbeteendet på SiC DMOSFET (plan) och UMOSFET (trench). För att undersöka detta användes en dubbelpulstest (DPT) mätuppställning både i simulering och experimentellt. Inverkan av grindinduktansen och motståndet på svängningsbeteendet i VGS under Millerperioden visade sig vara beroende av den övre anordningens tillstånd. Vidare upptäcktes att den övre anordningen hade en hög inverkan på svängningarna i VGS via dess parasitiska induktans. Gate-induktansen visade en blandad inverkan på IDS- och VDS-översvängning, med IDS-översvängning som minskade med ökande gateinduktans och det omvända fallet för VDS. Gatemotståndet visade dock en konsekvent inverkan på både IDS- och VDS-överskridningar, med båda minskande med ökande gatemotstånd. Dessa resultat pekar slutligen på inverkan av di/dt- och dv/dt-transienter. Ett intressant resultat som observerats på dessa grundorsaker visade att i det använda DPT-arrangemanget kan lägre testströmnivåer ha mer signifikant inverkan på svängningarna i VGS än högre testström vid variation av testströmmarna, med 20 A som har den högsta inverkan på svängningarna i simuleringar och 15 A som har störst effekt vid experimentell verifiering. På omkopplingsenergin visades inte grindinduktansen ha någon signifikant inverkan på omkopplingsförlusterna medan grindresistansen hade mycket mer betydande inverkan på omkopplingsförlusterna.

Organic coatings are extensively used as protective coatings in several industries including the automotive and aircraft industries. The last few years have witnessed an increased interest in improving not only the mechanical properties but also the corrosion protection properties of organic coatings. Among the currently investigated methods of improving the performance of organic coatings is the incorporation of additives in the organic paint matrix. Vapor grown carbon nanofibers (VGCNFs) are a class of carbon fibers that are produced by catalytic dehydrogenation of a hydrocarbon at high temperatures. Depending on the method of synthesis and the post-treatment processes, the diameter of the VGCNFs is normally in the 10-300 nm range. The small size, light weight, high aspect ratio, and unique physical, thermal, mechanical, and electrical properties of VGCNF make it an ideal reinforcing filler in polymer matrix nanocomposites to enhance the mechanical properties of the pure polymeric material in high performance applications in several industries such as the automotive, aircraft, battery, sensors, catalysis, electronics, and sports industries. The main objective of the current investigation was to study the corrosion protection offered by the incorporation of VGCNFs into a commercial alkyd paint matrix applied to the surface of mild steel coupons. The corrosion protection was investigated by immersing samples in air saturated 3% NaCl solution (artificial seawater). The samples were studied by electrochemical impedance spectroscopy (EIS) along with other measurements, including electrochemical (open circuit potential, cyclic voltammetry), chemical (salt spray test), electrical conductivity, and surface analysis (SEM, AFM, optical profilometry, and nanoindentation). The study involved the investigation of the effect of the weight percent (wt %) of the VGCNF as well as the coating film thickness on the corrosion protection performance of the coated steel samples when exposed to the corrosive electrolyte. By way of contrast, the EIS behavior of steel coupons coated with a paint coating incorporating different weight percents of powdered silicon carbide (SiC) particles was also studied. The EIS spectra were used to calculated and graph several corrosion parameters for the investigated systems. At the end, the studied coatings were ranked in order of their anticorrosive properties.