Master thesis work at ITN (Department of Science and Technology) in the areas of A/D-construction and RF-circuit design. Major goal of project were to research suitable possibilities for implementations of direct conversion in transceivers operating in the 160MHz band, theoretic study followed by development of components in the construction environment Cadence. Suitable A/D- converter and other important parts were selected at the end of the theoretic study. Subsampling technique was applied to make A/D sample requirements more realistic to achieve. Besides lowering requirements on A/D-converter it allows a more simple construction, which saves more components than subsampling adds. Subsampling add extra noise, because of that an A/D-converter based on the RSD algorithm was chosen to improve error rate. To achieve high bit-processing rate compared to the used number of transistors, pipeline structure were selected as conversion method. The receiver was that part which gained largest attention because it’s the part which is most interesting to optimise. A/D-conversion is more difficult to construct than D/A conversion, besides there’s more to gain from eliminating mixers in the receiver than in the transmitter.

The Decimator, an SED Systems Ltd. product, is a PCI slot card that performs both time and frequency domain measurements of given input signals. It is essentially a more economical version of a bench spectrum analyzer or oscilloscope, with a PC interface. Several issues limit the speed and accuracy of the results of the Decimator, and the study of these issues is the focus of this thesis. These issues, including but not limited to, are as follows: 1) Imbalances between the received In-phase and Quadrature-phase channels; 2) The FFT and Windowing functions are performed by a microcontroller, but it is desired that they be migrated to an FPGA. While solutions to improve the first issue is being implemented and verified, the second issue is not one of simply reducing a source of error. The second issue requires a cost-benefit analysis on the migration of these signal processing algorithms from an ARM microcontroller to a Xilinx FPGA.

In der vorliegenden Arbeit wird der Entwurf von Funkempfängern für digitale Modulation betrachtet. Dabei liegt der Schwerpunkt der Betrachtungen beim Finden einer geeigneten Empfängerarchitektur, der Spezifikation der einzusetzenden Bausteine, der Auswahl einer geeigneten Arbeitsfrequenz und eines passenden Modulationsverfahrens sowie der Festlegung einer dem Einsatzzweck angepaßten Datenrate. Ein wesentlicher Punkt ist die der Empfangsaufgabe angepaßte gewichtete Bekämpfung der auftretenden Störbeiträge. Dafür werden zunächst Grundlagen, wie wichtige Modulationsverfahren, Empfängerarchitekturen sowie Bestimmungsgleichungen für Parameter eingeführt. Darauf aufbauend wird eine allgemeingültige Methode zum Entwurf von Funkempfängern für digitale Modulation entwickelt. Diese Methode kann stets angewendet werden, wenn ein Empfänger für digitale Modulation entworfen werden soll. Wesentliche zu berücksichtigende Einsatzparameter und Randbedingungen werden an passender Stelle in den Entwurf einbezogen und eine entsprechend angepaßte Lösung wird weiterverwendet. Die Entwurfsmethode eignet sich sowohl für den freien Empfängerentwurf als auch für Entwürfe, die sich an der Einhaltung von Standards orientieren müssen. Der Kerngedanke besteht darin, das alle Störeinflüsse einen gleichgroßen Beitrag zur Signalverfälschung liefern sollen. Um dies zu erreichen, werden potentielle Störeinflüsse analysiert und entsprechend ihres Einflusses gewichtet zur weiteren Bestimmung der notwendigen Eigenschaften der Empfängerbaugruppen herangezogen. In der vorliegenden Arbeit wird hauptsächlich der allgemeine Anwendungsfall des freien nicht standardbezogenen Empfängerentwurfes betrachtet. Es wird aufgezeigt, wie durch die Analyse und entsprechende Berücksichtigung einer variablen Anzahl von Störeinflüssen die Eigenschaften der einzelnen Empfängerkomponenten jeweils bestmöglich eingestellt werden können. Diese Methode wird anschließend anhand von verschiedenartigen Beispielen weiter illustriert und ihre erfolgreiche Anwendbarkeit veranschaulicht. Anhand einer Mischerschaltung wird beispielhaft auf grundlegende Ansätze zur Verbesserung der Linearitätseigenschaften eingegangen. Dabei werden spezifische Unterschiede zwischen einer Superhet- bzw. einer Direktmischarchitektur hervorgehoben. Weiterhin wird eine Methode zur Wiederverwendung (Re-Use) von analogen Schaltungen oder ähnlichen Objekten vorgeschlagen. Dabei werden die Schaltungen anhand einer Vorgabe bewertet, und es wird eine Rangfolge aufgestellt. Damit ist gewährleistet, daß die der Vorgabe am besten entsprechende Schaltung gefunden werden kann, auch wenn eine 100%ige Übereinstimmung nicht gegeben ist. Die hierfür notwendigen Bewertungsalgorithmen werden ausführlich dargestellt und ihr jeweiliger Einsatz wird erläutert. Abschließend erfolgt eine überblicksweise Darstellung von Simulationswerkzeugen und -verfahren, die für den Empfängerentwurf bedeutsam sind. Dabei wird hauptsächlich auf die Verbindung von System- und Schaltungsentwurf eingegangen, und es werden bestehende Probleme dargelegt sowie vorhandene Lösungsmöglichkeiten aufgezeigt. Einige im Zusammenhang mit der Simulation interessante Modellierungsgesichtspunkte werden ebenfalls dargestellt.

Emerging technologies such as Bluetooth and 802.11b (Wi-Fi) have fuelled the growth of the short-range communication industry. Bluetooth, the leading WPAN (wireless personal area network) technology, was designed primarily for cable replacement applications. The first generation Bluetooth products are focused on providing low-cost radio connections among personal electronic devices. In the WLAN (wireless local area network) arena, Wi-Fi appears to be the superior product. Wi-Fi is designed for high speed internet access, with higher radio power and longer distances. Both technologies use the same 2.4GHz ISM band. The differences between Bluetooth and Wi-Fi standard features lead to a natural partitioning of applications. Nowadays, many electronics devices such as laptops and PDAs, support both Bluetooth and Wi-Fi standards to cover a wider range of applications. The cost of supporting both standards, however, is a major concern. Therefore, a dual-mode transceiver is essential to keep the size and cost of such system transceivers at a minimum. A fully integrated low-IF Bluetooth receiver is designed and implemented in a low cost, main stream 0.35um CMOS technology. The system includes the RF front end, frequency synthesizer and baseband blocks. It has -82dBm sensitivity and draws 65mA current. This project involved 6 Ph.D. students and I was in charge of the design of the channel selection complex filter is designed. In the Bluetooth transmitter, a frequency modulator with fine frequency steps is needed to generate the GFSK signal that has +/-160kHz frequency deviation. A low power ROM-less direct digital frequency synthesizer (DDFS) is designed to implement the frequency modulation. The DDFS can be used for any frequency or phase modulation communication systems that require fast frequency switching with fine frequency steps. Another contribution is the implementation of a dual-mode 802.11b/Bluetooth receiver in IBM 0.25um BiCMOS process. Direct-conversion architecture was used for both standards to achieve maximum level of integration and block sharing. I was honored to lead the efforts of 7 Ph.D. students in this project. I was responsible for system level design as well as the design of the variable gain amplifier. The receiver chip consumes 45.6/41.3mA and the sensitivity is -86/-91dBm.

Η περιοχή των ραδιοσυχνοτήτων (RF) για σχεδίαση ηλεκτρονικών κυκλωμάτων για τηλεπικοινωνιακά συστήματα αποτελεί ένα χώρο έντονης ερευνητικής δραστηριότητας. Το πρότυπο υπερευρείας ζώνης με την ονομασία Ultra Wideband (UWB), που καταλαμβάνει συχνότητες από 3.1-10.6 GHz, αποτέλεσε αντικείμενο της παρούσης έρευνας με σκοπό την σχεδίαση, κατασκευή και μέτρηση ολοκληρωμένων κυκλωμάτων με έμφαση στα κυκλώματα του μπροστινού τμήματος του UWB δέκτη. Η κατανόηση της λειτουργίας του πομποδέκτη και των παραμέτρων λειτουργίας σε επίπεδο συστήματος αποτέλεσε την αρχική προσέγγιση, με σκοπό τον καθορισμό των προδιαγραφών λειτουργίας των πιο κρίσιμων στοιχείων. Η ανάλυση έλαβε χώρα τόσο σε θεωρητικό επίπεδο όσο και σε επίπεδο εξομοίωσης και τα ηλεκτρονικά στοιχεία των υψηλών συχνοτήτων όπως είναι ο ενισχυτής χαμηλού θορύβου (Low Noise Amplifier - LNA) καθώς και ο μίκτης είναι τα πιο απαιτητικά στη σχεδίαση. Η έρευνα επικεντρώθηκε αρχικά στο κύκλωμα του ενισχυτή χαμηλού θορύβου , το οποίο ευρισκόμενο αμέσως μετά την κεραία λήψης, καλείται να ικανοποιήσει πολλές και αντικρουόμενες μεταξύ τους απαιτήσεις όσον αφορά το εύρος ζώνης, το κέρδος, την κατανάλωση ενέργειας και επιφανείας πυριτίου και το θόρυβο. Στα πλαίσια της μελέτης εξερευνήθηκαν και αξιολογήθηκαν οι υφιστάμενες τοπολογίες που έχουν εμφανιστεί στη βιβλιογραφία και επιλέχθηκαν δύο από αυτές για περεταίρω διερεύνηση. Το πρώτο ολοκληρωμένο που κατασκευάστηκε περιλαμβάνει τρεις ενισχυτές, οι δύο από αυτούς χρησιμοποιούν την τοπολογία κοινής πηγής με φίλτρο εισόδου και πηνίο στην πηγή (inductive source degeneration) και διαφέρουν στον τρόπο μέτρησης, όπου ο ένας ενισχυτής μετράται πάνω στο ολοκληρωμένο (on-wafer probing) και ο έτερος τοποθετείται σε πλακέτα (chip on board). Με τον τρόπο αυτό αποκτάται διαίσθηση όσον αφορά την επίδραση των παρασιτικών που υπεισέρχονται εξαιτίας των διασυνδέσεων των αγωγών (bondwires) μεταξύ ολοκληρωμένου και πλακέτας. Ταυτόχρονα για τον συγκεκριμένο ενισχυτή εφαρμόζεται και στρατηγική προστασίας από ηλεκτροστατικά φορτία (ESD). Ο τρίτος ενισχυτής βασίζεται στην τοπολογία ανάδρασης και αποτέλεσε προϊόν πρωτότυπης έρευνας και χρησιμοποιήθηκαν τεχνικές διεύρυνσης του εύρους ζώνης λειτουργίας με χρήση επαγωγικών στοιχείων. Οι μετρήσεις που επακολούθησαν την κατασκευή αποδείχθηκαν επιτυχείς και κατά κανόνα υπήρξε σύγκλιση με την εξομοίωση. Ο τρίτος ενισχυτής παρουσιάζει την πιο ανταγωνιστική απόδοση και είναι ικανός να λειτουργήσει μέχρι τα 7GHz. Επακόλουθο της κυκλωματικής μελέτης των ενισχυτών χαμηλού θορύβου υπήρξε η εστίαση σε επίπεδο συστήματος για την κατασκευή του συνολικού RF τμήματος του δέκτη σε ολοκληρωμένο και για λειτουργία μέχρι τα 10.6GHz. Το σύστημα περιλαμβάνει τον LNA της τοπολογίας με ανάδραση και στη συνέχεια δύο πανομοιότυπα μονοπάτια αποτελούμενα το καθένα από μίκτη, υψιπερατό φίλτρο και απομονωτή εξόδου στα 50 Ω για τις ανάγκες της μέτρησης. Ως κύριες προκλήσεις ανέκυψαν ο σχεδιασμός του μίκτη και κυρίως της διεπαφής με τον LNA, ο οποίος παρέχει σήμα μονής εξόδου ενώ ο μίκτης λειτουργεί διαφορικά. Στα πλαίσια της διατριβής προτάθηκε μια τεχνική για κύκλωμα μετατροπής μονού σε διαφορικό σήμα (balun), η οποία συνδυαζόμενη με την τοπολογία του μίκτη που επελέγη, ουσιαστικά ενσωματώνεται στο μίκτη και παρέχει διαφορικά σήματα με πολύ καλή ακρίβεια στο πλάτος και τη φάση. Το balun βασίζεται στην τοπολογία του διαφορικού ζεύγους και επεκτείνει πάνω σε αυτήν με χρήση πηνίου που στο κέντρο του παρέχει έναν τρίτο ακροδέκτη διασύνδεσης στην τροφοδοσία. Καταυτόν τον τρόπο λαμβάνει χώρα σύζευξη μεταξύ των φορτίων του balun που εγγυάται την ακρίβεια των μεγεθών που προαναφέρθηκαν. Η τεχνική υποστηρίζεται από ενδελεχή μαθηματική ανάλυση και παρουσιάζονται συγκρίσεις μεταξύ θεωρίας και εξομοίωσης με σύγκλιση μεταξύ των. Ο μίκτης που κατέληξε η έρευνα ανήκει στην κατηγορία της συνδεσμολογίας folded cascode. Δεδομένων επίσης των περιορισμών που υπήρχαν στον εξοπλισμό μέτρησης εφαρμόστηκαν τεχνικές με πιο σημαντική την τροφοδότηση των σημάτων ταλαντωτή τα οποία εσωτερικά του ολοκληρωμένου μετατρέπονται σε διαφορικά και καθοδηγούνται για αποφυγή ασυμμετριών σε ισομήκης μεταλλικές γραμμές μεταφοράς. Σε όλα τα κρίσιμα σημεία έχει προβλεφτεί στρατηγική θωράκισης των υψίσυχνων σημάτων ενώ η τοποθέτηση ενός πολύ μεγάλου αριθμού στοιχείων στο πυρίτιο υπήρξε προϊόν συγκερασμού διαφορετικών απαιτήσεων στη χωροταξία τους με πολυάριθμες τεχνικές και εμπειρικούς κανόνες να έχουν εφαρμοστεί. Η τελική προτεινόμενη αρχιτεκτονική τύπου άμεσης μετατροπής παρόλα τα σχεδιαστικά ρίσκα που είχαν ληφθεί, λειτούργησε επιτυχώς μέχρι και τα 8.5GHz επισφραγίζοντας την συνολική προσπάθεια. / The domain of RF engineering for electronic circuits, targeting the application of telecommunication systems, constitutes a field of intense research activities. The UWB protocol that occupies a frequency spectrum between 3.1 and 10.6 GHz is the subject of the current work which aims to the design, fabrication and measurement of electronic circuits with emphasis put on the receiver’s RF front end. The initial focus of the research work targets the Low Noise Amplifier (LNA) circuit, a demanding and challenging circuit that being at the very front of the receiver’s chain, has to compromise among different and contradictory requirements, namely the extended bandwidth, the gain, the power and chip area consumption and the noise performance. Existing topologies in the literature were explored and classified and two among them were selected for further research. The first fabricated chip includes three LNAs, two of which apply the common source topology with input bandpass filter and inductive source degeneration and their difference lies in the measurement method. One amplifier is measured on wafer while the other is mounted on board. That way, intuition is acquired regarding the effect of the bondwires that act as the interface between the chip and the board. At the same time, ESD protection strategy is applied as the chip is more vulnerable to static currents. The third LNA is based on the feedback topology and constitutes a work of novelty, where bandwidth extension techniques were applied, comprising of inductive elements. The following measurement procedure was successful indicating an upper frequency of operation for the feedback LNA up to 7GHz. The focus of the work after the LNAs was shifted to system level for the implementation of the total RF front end of the receiver up to 10.6GHz. The system comprises an improved version of the feedback LNA followed by two identical paths, each one consisting of a mixer, a high pass filter and an output buffer at 50 Ohm for measurement purpose. The challenges that are mostly highlighted are the mixer design in conjunction with the necessary balun interface from the single ended output of the LNA to the differential mixer. A novel technique is proposed for the balun that builds on the differential pair topology and provides coupling between the load elements that both are implemented with a center tapped inductor. That way the designed balun achieves balanced outputs in terms of amplitude and phase. The technique is supported by mathematical analysis and the comparison between computed and simulated results show convergence. The resulting mixer that includes the balun belongs to the folded cascode differential connection. Moreover, given the limitations of the available measurement equipment, several layout techniques were applied; particularly in the issue of the external LO signal feeding. The two quadrature LO signals are provided in single ended form and traverse the chip by two equal length transmission lines that are separated at the center of the chip and reach the on chip single to differential converters that are placed close to the mixers. In every critical point, care is taken to shield the high frequency signals from interferences. In any case, the placing of a high number of individual elements that have different requirements on the same chip requires for compromises, while layout techniques and rules of thumb have been applied to the maximum extend. The final proposed architecture belongs to the direct conversion category and worked successfully up to the frequency of 8.5GHz. It achieves gain of 25dB, double sideband noise figure of 7dB and power consumption of 62.7 mW.

Os requisitos de linearidade e ruído em aplicações multi-banda e multi-protocolo fazem que o projeto de misturadores RF seja uma tarefa muito desafiadora. Nesta dissertação dois misturadores com base na topologia célula de Gilbert são propostas. Linearidade e ruído foram as principais figuras de mérito consideradas para o misturadores propostos. Para aumento linearidade, foi utilizada uma técnica de cancelamento de harmônicas pós-distorção (PDHC). E, para redução de ruído, foi utilizado um circuito de redução dinâmica de corrente combinada com um filtro LC sintonizado na frequência do LO e cancelamento de ruído térmico. A análise por séries Volterra do estágio transcondutância do misturador proposto é reportada para mostrar a eficácia da técnica de cancelamento de harmônicos com pósdistorção. O circuito de linearização adicionado não aumenta o tamanho do misturador, nem degrada ganho de conversão, figura de ruído, ou consumo de potência. Simulações elétricas foram realizadas em nível de pós-layout para a primeira topologia e nível esquemático para a segunda topologia, usando processo CMOS de 0.13 mm da IBM. As melhorias em IIP2 e IIP3 são apresentadas em comparação com o misturador do tipo célula de Gilbert convencional. Para a primeira topologia, foi obtido um ganho de conversão de 10.2 dB com uma NF de 12 dB para o misturador projetado funcionando a 2 GHz, com uma frequência intermediária de 500 kHz. E um IIP2 e IIP3 de 55 dBm e 10.9 dBm, respectivamente, consumindo apenas 5.3 mW de uma fonte de 1.2 V. Para a segunda topologia, foram obtidos um ganho de conversão de [13.8 ~11] dB, um coeficiente de reflexão na entrada (S11) de [-18 ~-9.5] dB e um NF de [8.5 ~11] dB no intervalo de 1 a 6 GHz. Para as especificações de linearidade, um valor médio de IIP3 de 0 dBm foi alcançado para toda a faixa de frequência, consumindo 19.3 mW a partir de uma fonte de 1.2 V. Especificações adequadas para operação multi-banda e multi-protocolo. / The linearity and noise requirements in multi-band multi-standard applications make the design of RF CMOS mixers a very challenging task. In this dissertation two downconversion mixers based on the Gilbert-cell topology are proposed. Linearity and noise were the principal figures of merit for the proposed mixers. For linearity improvement, post distortion harmonic cancellation (PDHC) was employed. And, for noise reduction, dynamic current injection combined with an LC filter tuned at the LO frequency and thermal-noise cancellation were used. A Volterra series analysis of the transconductance stage is reported to show the effectiveness of the post-distortion harmonic cancellation technique. The added linearization circuitry does not increase the size of the mixer, nor does it degrade conversion gain, noise figure, or power consumption. Electrical simulations were performed on extracted layout level from the first topology and schematic level from the second topology. Using an IBM 0.13 mm CMOS process improvements on IIP3 and IIP2 in comparison to the conventional Gilbert-cell mixer are demonstrated. For the first topology, we achieved a conversion gain of 10.2 dB with a NF of 12 dB for the designed mixer working at 2 GHz, with a low-IF of 500 kHz and an IIP2 and IIP3 of 55 dBm and 10.9 dBm, respectively, while consuming only 5.3 mW from a 1.2 V supply. For the second topology, we achieved a conversion gain range of [13.8 ~11] dB, an input reflection coefficient (S11) of [-18 ~-9.5] dB and a NF of [8.5 ~11] dB in the frequency range of 1 to 6 GHz. For the linearity specs, an IIP3 of 0 dBm was achieved for the whole frequency range, while consuming 19.3 mW from a 1.2 V supply, making the second topology well suited for multi-band and multi-standard operation.

Os requisitos de linearidade e ruído em aplicações multi-banda e multi-protocolo fazem que o projeto de misturadores RF seja uma tarefa muito desafiadora. Nesta dissertação dois misturadores com base na topologia célula de Gilbert são propostas. Linearidade e ruído foram as principais figuras de mérito consideradas para o misturadores propostos. Para aumento linearidade, foi utilizada uma técnica de cancelamento de harmônicas pós-distorção (PDHC). E, para redução de ruído, foi utilizado um circuito de redução dinâmica de corrente combinada com um filtro LC sintonizado na frequência do LO e cancelamento de ruído térmico. A análise por séries Volterra do estágio transcondutância do misturador proposto é reportada para mostrar a eficácia da técnica de cancelamento de harmônicos com pósdistorção. O circuito de linearização adicionado não aumenta o tamanho do misturador, nem degrada ganho de conversão, figura de ruído, ou consumo de potência. Simulações elétricas foram realizadas em nível de pós-layout para a primeira topologia e nível esquemático para a segunda topologia, usando processo CMOS de 0.13 mm da IBM. As melhorias em IIP2 e IIP3 são apresentadas em comparação com o misturador do tipo célula de Gilbert convencional. Para a primeira topologia, foi obtido um ganho de conversão de 10.2 dB com uma NF de 12 dB para o misturador projetado funcionando a 2 GHz, com uma frequência intermediária de 500 kHz. E um IIP2 e IIP3 de 55 dBm e 10.9 dBm, respectivamente, consumindo apenas 5.3 mW de uma fonte de 1.2 V. Para a segunda topologia, foram obtidos um ganho de conversão de [13.8 ~11] dB, um coeficiente de reflexão na entrada (S11) de [-18 ~-9.5] dB e um NF de [8.5 ~11] dB no intervalo de 1 a 6 GHz. Para as especificações de linearidade, um valor médio de IIP3 de 0 dBm foi alcançado para toda a faixa de frequência, consumindo 19.3 mW a partir de uma fonte de 1.2 V. Especificações adequadas para operação multi-banda e multi-protocolo. / The linearity and noise requirements in multi-band multi-standard applications make the design of RF CMOS mixers a very challenging task. In this dissertation two downconversion mixers based on the Gilbert-cell topology are proposed. Linearity and noise were the principal figures of merit for the proposed mixers. For linearity improvement, post distortion harmonic cancellation (PDHC) was employed. And, for noise reduction, dynamic current injection combined with an LC filter tuned at the LO frequency and thermal-noise cancellation were used. A Volterra series analysis of the transconductance stage is reported to show the effectiveness of the post-distortion harmonic cancellation technique. The added linearization circuitry does not increase the size of the mixer, nor does it degrade conversion gain, noise figure, or power consumption. Electrical simulations were performed on extracted layout level from the first topology and schematic level from the second topology. Using an IBM 0.13 mm CMOS process improvements on IIP3 and IIP2 in comparison to the conventional Gilbert-cell mixer are demonstrated. For the first topology, we achieved a conversion gain of 10.2 dB with a NF of 12 dB for the designed mixer working at 2 GHz, with a low-IF of 500 kHz and an IIP2 and IIP3 of 55 dBm and 10.9 dBm, respectively, while consuming only 5.3 mW from a 1.2 V supply. For the second topology, we achieved a conversion gain range of [13.8 ~11] dB, an input reflection coefficient (S11) of [-18 ~-9.5] dB and a NF of [8.5 ~11] dB in the frequency range of 1 to 6 GHz. For the linearity specs, an IIP3 of 0 dBm was achieved for the whole frequency range, while consuming 19.3 mW from a 1.2 V supply, making the second topology well suited for multi-band and multi-standard operation.

Os requisitos de linearidade e ruído em aplicações multi-banda e multi-protocolo fazem que o projeto de misturadores RF seja uma tarefa muito desafiadora. Nesta dissertação dois misturadores com base na topologia célula de Gilbert são propostas. Linearidade e ruído foram as principais figuras de mérito consideradas para o misturadores propostos. Para aumento linearidade, foi utilizada uma técnica de cancelamento de harmônicas pós-distorção (PDHC). E, para redução de ruído, foi utilizado um circuito de redução dinâmica de corrente combinada com um filtro LC sintonizado na frequência do LO e cancelamento de ruído térmico. A análise por séries Volterra do estágio transcondutância do misturador proposto é reportada para mostrar a eficácia da técnica de cancelamento de harmônicos com pósdistorção. O circuito de linearização adicionado não aumenta o tamanho do misturador, nem degrada ganho de conversão, figura de ruído, ou consumo de potência. Simulações elétricas foram realizadas em nível de pós-layout para a primeira topologia e nível esquemático para a segunda topologia, usando processo CMOS de 0.13 mm da IBM. As melhorias em IIP2 e IIP3 são apresentadas em comparação com o misturador do tipo célula de Gilbert convencional. Para a primeira topologia, foi obtido um ganho de conversão de 10.2 dB com uma NF de 12 dB para o misturador projetado funcionando a 2 GHz, com uma frequência intermediária de 500 kHz. E um IIP2 e IIP3 de 55 dBm e 10.9 dBm, respectivamente, consumindo apenas 5.3 mW de uma fonte de 1.2 V. Para a segunda topologia, foram obtidos um ganho de conversão de [13.8 ~11] dB, um coeficiente de reflexão na entrada (S11) de [-18 ~-9.5] dB e um NF de [8.5 ~11] dB no intervalo de 1 a 6 GHz. Para as especificações de linearidade, um valor médio de IIP3 de 0 dBm foi alcançado para toda a faixa de frequência, consumindo 19.3 mW a partir de uma fonte de 1.2 V. Especificações adequadas para operação multi-banda e multi-protocolo. / The linearity and noise requirements in multi-band multi-standard applications make the design of RF CMOS mixers a very challenging task. In this dissertation two downconversion mixers based on the Gilbert-cell topology are proposed. Linearity and noise were the principal figures of merit for the proposed mixers. For linearity improvement, post distortion harmonic cancellation (PDHC) was employed. And, for noise reduction, dynamic current injection combined with an LC filter tuned at the LO frequency and thermal-noise cancellation were used. A Volterra series analysis of the transconductance stage is reported to show the effectiveness of the post-distortion harmonic cancellation technique. The added linearization circuitry does not increase the size of the mixer, nor does it degrade conversion gain, noise figure, or power consumption. Electrical simulations were performed on extracted layout level from the first topology and schematic level from the second topology. Using an IBM 0.13 mm CMOS process improvements on IIP3 and IIP2 in comparison to the conventional Gilbert-cell mixer are demonstrated. For the first topology, we achieved a conversion gain of 10.2 dB with a NF of 12 dB for the designed mixer working at 2 GHz, with a low-IF of 500 kHz and an IIP2 and IIP3 of 55 dBm and 10.9 dBm, respectively, while consuming only 5.3 mW from a 1.2 V supply. For the second topology, we achieved a conversion gain range of [13.8 ~11] dB, an input reflection coefficient (S11) of [-18 ~-9.5] dB and a NF of [8.5 ~11] dB in the frequency range of 1 to 6 GHz. For the linearity specs, an IIP3 of 0 dBm was achieved for the whole frequency range, while consuming 19.3 mW from a 1.2 V supply, making the second topology well suited for multi-band and multi-standard operation.

The advent of high-fT silicon CMOS/BiCMOS technologies has led to a dramatic upsurge in the research and development of radio and microwave frequency integrated circuits (ICs) in silicon. The integration of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) into established "digital" CMOS processes has provided analog performance in silicon that is not only competitive with III-V compound-semiconductor technologies, but is also potentially lower in cost. Combined with improvements in silicon on-chip passives, such as high-Q metal-insulator-metal (MIM) capacitors and monolithic spiral inductors, these advanced RF CMOS and SiGe BiCMOS technologies have enabled complete silicon-based RF integrated circuit (RFIC) solutions for emerging wireless communication standards; indeed, both the analog and digital functionalities of an entire wireless system can now be combined in a single IC, also known as a wireless "system-on-a-chip" (SoC). This approach offers a number of potential benefits over multi-chip solutions, such as reductions of parasitics, size, power consumption, and bill-of-materials; however, a number of critical challenges must be considered in the integration of such SoC solutions. The focus of this research is the application of SiGe BiCMOS technology to on-going challenges in the development of receiver components for high speed wireless data networks. The research seeks to drive SoC integration by investigating circuit topologies that eliminate the need for off-chip components and are amenable to complete on-chip integration. The first part of this dissertation presents the design, fabrication, and measurement of a 5--6GHz sub-harmonic direct-conversion-receiver (DCR) front-end, implemented in the IBM 0.5um 5HP SiGe BiCMOS process. The design consists of a fully-differential low-noise amplifier (LNA), a set of quadrature (I and Q)x~2 sub-harmonic mixers, and an LO conditioning chain. The front-end design provides a means to address performance limitations of the DCR architecture (such as DC-offsets, second-order distortion, and quadrature phase and amplitude imbalances) while enabling the investigation of high-frequency IC design complications, such as package parasitics and limited on-chip isolation. The receiver front-end has a measured conversion gain of ~18dB, an input second-order intercept point of +17.5dBm, and a noise figure of 7.2dB. The quadrature phase balance at the sub-harmonic mixer IF outputs was measured in the presence of digital switching noise; 90<degree> balance was achieved, over a specific range of LO power levels, with a square wave noise signal injected onto the mixer DC supply rails. The susceptibility of receiver I/Q balance to mixed-signal effects in a SoC environment motivates the second part of this dissertation --- the design of a phase and amplitude tunable, quadrature voltage-controlled oscillator (QVCO) for the on-chip synthesis of quadrature signals. The QVCO design, implemented in the Freescale (formerly Motorola) 0.18um SiGe:C RFBiCMOS process, uses two identical, differential LC-tank VCOs connected such that the two oscillator outputs lock in quadrature to the same frequency. The QVCO designs proposed in this work provide the additional feature of phase-tunability, i.e. the relative phase balance between the quadrature outputs can be adjusted dynamically, offering a simulated tuning range of ~90<degree>+/-10â ¹degree> in addition, a variable-gain buffer/amplifier circuit that provides amplitude tunability is introduced. One potential application of the QVCO is in a self-correcting RF receiver architecture, which, using the phase and amplitude tunability of the QVCO, could dynamically adjust the IF output quadrature phase and amplitude balance, in near real-time, in the analog-domain. The need for high-quality inductors in both the DCR and QVCO designs motivates the third aspect of this dissertation --- the characterization and modeling of on-chip spiral inductors with patterned ground shields, which are placed between the inductor coil and the underlying substrate in order to improve the inductor quality factor (Q). The shield prevents the coupling of energy away from the inductor spiral to the typically lossy Si substrate, while the patterning disrupts the flow of induced image currents within the shield. The experimental effort includes the fabrication and testing of a range of inductors with different values, and different types of patterned ground shields in different materials. Two-port measurements show a ~50% improvement in peak-Q and a ~20% degradation in self-resonant frequency for inductors with shields. From the measured results, a scalable lumped element model is developed for the rapid simulation of spiral inductors with and without patterned ground shields. The knowledge gained from this work can be combined and applied to a range of future RF/wireless SoC applications. The designs developed in this dissertation can be ported to other technologies (e.g. RF CMOS) and scaled to other frequency ranges (e.g. 24GHz ISM band) to provide solutions for emerging applications that require low-cost, low-power RF/microwave circuit implementations. / Ph. D.

The functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each standard has its own requirements for linearity and noise figure, and each standard operates at a different RF carrier frequency, implementing such a receiver is very challenging. Such a receiver could be theoretically implemented using a broadband mixing receiver or by direct sampling by a high-speed analog-to-digital converter (ADC). Broadband mixing requires the use of a harmonic rejection mixer (HRM) or tunable band pass filter to remove harmonic mixing effects, which in the past have suffered from a large primary clock tuning range and high power consumption. However, direct sampling of the RF input requires a high-speed ADC with large dynamic range which is typically limited by clock timing skew, clock jitter, or harmonic folding. In this dissertation, techniques for programmable broadband radio receivers are proposed. A local oscillator (LO) synthesis method within HRMs is proposed which reduces the required primary clock tuning range in broadband receivers. The LO synthesis method is implemented in 130-nm CMOS. A clocking technique is introduced within the two-stage HRM, which helps in achieving state-of-the-art harmonic rejection performance without calibration or harmonic filtering. An analog frequency synthesis based broadband channelizer is proposed using the LO synthesis method which is capable of channelizing a broadband input using a single mixing stage and primary clock frequency. A frequency-folded ADC architecture is proposed which enables high-speed sampling with high dynamic range. A receiver based on the frequency-folded ADC architecture is implemented in 65-nm CMOS and achieves a sample rate of 2-GS/s, a mean 49-dB SNDR, and 8.5-dB NF. / text