Les récentes avancées des applications de télécommunication radio-fréquences (RF), l'augmentation des fréquences d'opération des microprocesseurs et les possibilités de stockage de données rapides ont pour conséquence une expansion exponentielle du volume de données échangées. Ce développement a été permis et a engendré une demande croissante de systèmes de télécommunication de plus en plus performants, que ce soit en terme de débit, de flexibilité des réseaux, et bien évidement de coût des systèmes.<br /><br />Tous les systèmes de communication modernes requièrent un signal périodique stable pour fournir une base de temps nécessaire à la synchronisation, à l'alignement des horloges d'échantillonnage, à la récupération d'horloge ou encore à la synthèse de fréquence. Le verrouillage de phase est une des principales techniques pour répondre à ces besoins.<br /><br />L'enjeu de ce travail de thèse est de concevoir, réaliser et caractériser une boucle à verrouillage de phase capable de s'intégrer dans un système de télécommunication développé en partenariat entre la société STMicroelectronics et l'Institut Matériaux Microélectronique Nanosciences de Provence (IM2NP). Ce système faible coût, faible consommation, réalisé en technologie CMOS est destiné à des applications de type réseaux personnels sans fils. Des contraintes fortes en terme de surface silicium, consommation, réactivité de la boucle et de précision fréquentielle sont les éléments directeurs de la conception de cette PLL. La boucle réalisée devra être capable de fonctionner en synthétiseur de fréquence et en modulateur FSK. Une attention particulière sera portée à l'oscillateur contrôlé en tension, véritable coeur de la PLL proposée.

<p>Den här högskoleavhandlingen beskriver designen av ett IF-filter samt hårdvarukonstruktion av en ny 77 GHz FMCW-radar demonstrator. Syftet med demonstratorn är att illustrera hur kisel germanium-, SiGe, teknologi kan användas istället för den mer vedertagna men dyrare gallium arsenik-, GaAs, teknologin. Den gamla radar-prototypen vilken Acreo AB utvecklat är funktionell men behöver konstrueras om för att bättre kunna utvärdera radarprestandan. I avhandlingen presenteras grundläggande radarteori och ekvationer för att underlätta förståelsen av de olika systemblocken. Rapporten beskriver också systemarkitekturen och hur dess funktionalitet kommer att testas. Det omdesignade IF-filtret har simulerats i en PSpice-simulator och ett prototypkort av detta har tillverkats för mätningar. Ett 4-lagers kretskort av hela systemet har tagits fram i Orcad Layout. Slutligen innehåller rapporten förslag på förbättringar till nästa demonstratorversion.</p> / <p>This bachelor thesis describes the design of an IF-filter and the hardware construction of a new version of a 77 GHz FMCW-radar demonstrator. The purpose of the demonstrator is to illustrate how the silicon germanium-, SiGe, technology could be used instead of the more conventional but also much more expensive gallium arsenide-, GaAs, technology. The old radar prototype that Acreo AB has developed is fully functional but needs to be redesigned to be able to evaluate the radar performance in a better way. The thesis presents the basic radar theory and equations to help understanding the construction of the system blocks. The report also describes the system architecture and how its functionality should be tested. The redesigned IF-filter has been simulated in a PSpice simulator and a prototype has been manufactured and measured. A 4-layer PCB-board of the whole system was done in Orcad Layout. Finally the report is concluded with suggestions on improvements for the next demonstrator version.</p>

The objective of this dissertation is to develop key components of a CMOS heterodyne millimeter-wave receiver front end. Robust designs are necessary to overcome PVT variations as well as modeling inaccuracies, while with minimum power consumption overhead to facilitate low-power radio for portable applications. Heterodyne receiver topology is adopted because of its robust performances at millimeter-wave frequencies. Device models for both passive and active devices are developed and used in the circuit designs in this dissertation. Two low-noise amplifiers (LNAs) are developed in this dissertation. The first LNA features a proposed temperature-compensation biasing technique, which confines the gain variation within 5 dB for temperature variation from -5 to 85 Celsius degree. The measured gain and NF are 21 and 6.5 dB, respectively, for 49-mW power dissipation. The second LNA reveals a design technique to tolerate a low-accuracy model at millimeter-wave frequencies. Both LNAs provide full coverage of the FCC 60-GHz band (57-64 GHz). For the frequency generation circuits, both the IF QVCO and mm-wave VCO are investigated. The inherent bimodal oscillation of QVCOs is analyzed and, for the first time, a systematic measurement technique is proposed to intentionally control the oscillation mode. This technique is further utilized to extend the tuning range of the QVCO, which possesses dual tuning curves without penalty on phase noise. The measurement results of a 13-GHz QVCO in 90-nm CMOS reveals a 21.4% tuning range for continuously tuning from 11.7 to 14.5 GHz. The measured phase noise is -108 dBc/Hz at 1 MHz offset with a core power consumption of 10.8 mW. A millimeter-wave VCO is designed and fabricated in 65-nm CMOS. The VCO is fully characterized under voltage stress to examine the hot-carrier injection effects affecting the performance of a millimeter-wave VCO. The 41.6-47.4 GHz VCO is further integrated into a millimeter-wave down converter. The power-hungry buffer amplifiers are neglected by proper floor planning. Conversion loss of 1.4 dB is obtained with total power consumption of 72.5 mW. Lastly, a power management system consisting of low-dropout (LDO) regulators is designed and integrated in a 90-nm CMOS millimeter-wave transceiver to provide stable and low-noise supply voltages. Voltage variation issues are alleviated by the LDOs.

Den här högskoleavhandlingen beskriver designen av ett IF-filter samt hårdvarukonstruktion av en ny 77 GHz FMCW-radar demonstrator. Syftet med demonstratorn är att illustrera hur kisel germanium-, SiGe, teknologi kan användas istället för den mer vedertagna men dyrare gallium arsenik-, GaAs, teknologin. Den gamla radar-prototypen vilken Acreo AB utvecklat är funktionell men behöver konstrueras om för att bättre kunna utvärdera radarprestandan. I avhandlingen presenteras grundläggande radarteori och ekvationer för att underlätta förståelsen av de olika systemblocken. Rapporten beskriver också systemarkitekturen och hur dess funktionalitet kommer att testas. Det omdesignade IF-filtret har simulerats i en PSpice-simulator och ett prototypkort av detta har tillverkats för mätningar. Ett 4-lagers kretskort av hela systemet har tagits fram i Orcad Layout. Slutligen innehåller rapporten förslag på förbättringar till nästa demonstratorversion. / This bachelor thesis describes the design of an IF-filter and the hardware construction of a new version of a 77 GHz FMCW-radar demonstrator. The purpose of the demonstrator is to illustrate how the silicon germanium-, SiGe, technology could be used instead of the more conventional but also much more expensive gallium arsenide-, GaAs, technology. The old radar prototype that Acreo AB has developed is fully functional but needs to be redesigned to be able to evaluate the radar performance in a better way. The thesis presents the basic radar theory and equations to help understanding the construction of the system blocks. The report also describes the system architecture and how its functionality should be tested. The redesigned IF-filter has been simulated in a PSpice simulator and a prototype has been manufactured and measured. A 4-layer PCB-board of the whole system was done in Orcad Layout. Finally the report is concluded with suggestions on improvements for the next demonstrator version.

A fully integrated CMOS 0 – 900 phase shifter in 0.18um TSMC technology is presented. With the increasing use of wireless systems in GHz range, there is high demand for integrated phase shifters in phased arrays and MIMO on chip systems. Integrated phase shifters have quite a high number of integrated inductors which consume a lot of area and introduce a huge amount of loss which make them impractical for on chip applications. Also tuning the phase shift is another concern which seems difficult with use of passive elements for integrated applications. This work is presents a new method for implementing phase shifters using only active CMOS elements which dramatically reduce the occupied area and make the tuning feasible. Also a fully integrated millimeter-wave VCO is implemented using the same technology. This VCO can be part of a 24 GHz frequency synthesizer for 24 GHz ISM band transceivers. The 24 GHz ISM band is the unlicensed band and available for commercial communication and automotive radar use, which is becoming attractive for high bandwidth data rate.

In this thesis, a low phase noise local oscillator operating at 2210 MHz is designed and implemented to be used in X-Band transmitter of a LEO satellite. Designed local oscillator is a PLL (Phase Locked Loop) based frequency synthesizer which is implemented using discrete commercial components including ultra low noise voltage controlled oscillator and high resolution, low noise fractional-N synthesizer. Operational settings of the synthesizer are done using three wire serial interface of a microcontroller. Although there are some imperfections in the implementation, phase noise of the prototype system is pretty good which is measured as -123.2 dBc/Hz at 100 kHz offset and less than -141.3 dBc/Hz at 1 MHz offset. Made up of discrete components, the VCO used in the designed local oscillator is not integrable to frequency synthesizer which is implemented in CMOS technology. Considering technological progress, integrabilitiy of system components becomes important for designing single chip complete systems like transmitters, receivers or transceivers. Therefore considering a potential single chip transceiver production, also a CMOS voltage controlled oscillator is designed using standard TSMC 0.18um technology operating in between 2.05 GHz and 2.35 GHz . Since low phase noise is the main concern, phase noise models and phase noise reduction techniques that are derived from the models are studied. These techniques are applied to the VCO core to see the effects. Design is finalized by applying some of those techniques which are found to be noticeably effective to the core design. Finalized core operates from 2.15 GHz to 2.25 GHz and phase noise is simulated as -107.265 dBc/Hz at 100 kHz offset and -131.167 dBc/Hz at 1 MHz offset. Also oscillator has figure of merit of -185.4 at 100 kHz offset. These values show that designed core is considerably good when compared to similar designs.

L'objectif de cette thèse est de démontrer la faisabilité d'oscillateurs contrôlés en tension (O.C.T.) rivalisant en termes de bruit de phase avec les O.C.T. fabriqués en technologies III V. Cet O.C.T. doit être complètement intégré, adresser la bande Ku et utiliser la technologie QUBiC4X de NXP Semiconductors. Les travaux de cette thèse sont articulés autour de trois chapitres principaux, le premier revient sur les bases fondamentales à la compréhension des phénomènes inhérents aux composants électroniques et présents dans les oscillateurs plus particulièrement. Le second explique, en s'appuyant sur l'analyse des formes d'ondes et sur des calculs analytiques, les choix retenus en termes d'architecture pour la partie active ainsi que pour le résonateur afin de minimiser la conversion du bruit AM/PM et atteindre les meilleures performances possibles en bruit de phase. Il décrit les quatre versions d'O.C.T. réalisés et analyse les résultats de simulations post-layout obtenus pour justifier leur fabrication. Il présente notamment une architecture innovante utilisant les avantages d'un montage cascode ainsi qu'un résonateur à trois inductances différentielles imbriquées les unes dans les autres. Le troisième chapitre détaille les choix de design faits lors du dessin des masques ainsi que les résultats de mesures obtenus pour les quatre versions fabriquées. Enfin, il se termine par une énumération des recherches menées dans le but d'expliquer les différences observées entre les résultats de mesure et de simulation. / The thesis goal is to demonstrate the feasibility of voltage controlled oscillator (VCO) challenging the VCOs using III-V technologies regarding phase noise performances. This VCO must be fully integrated, target the Ku-band and use the QUBiC4X process from NXP Semiconductors. This thesis work is based on three main chapters, the first one reviews the fundamentals to understand the intrinsic phenomena in electronics components and more particularly in oscillators. The second explains, by using the waveforms analysis and analytical demonstrations, the choices made regarding both the active part and the resonator architecture in order to minimize the AM/PM noise conversion and then to reach the best phase noise performances. It describes the four versions of the realized VCOs and analyzes the post-layout simulations results to justify their fabrications. It shows more specifically an innovative architecture using the advantages of a cascode configuration and a resonator based on three interlocked differential inductors. Finally, the third chapter focuses on the masks' layout and measurements results of the four VCOs. It also details the investigations made to explain the differences between measurements and simulations.

Advanced achievements in the area of RF circuit design led to a significant increase in availability of wireless communications in everyday life. However, the rapid growth in utilizing the RF equipment has brought several challenges in different aspects of RF circuit design. This has been motivating researchers to introduce solution to cope with these challenges and further improve the performance of the RF circuits. In this dissertation, we focus on the improvements in three aspects of the circuit design. High temperature and temperature compensated transmitter design, ultra-low phase noise signal generators, and compact and low complexity polar transmitter design. Increase in the ambient temperature can impact the performance of the entire communication system. However, the RF hardware is main part of the system that is under the impact of the temperature variations in which it can change the characteristics of the individual building blocks of the RF chain. Moreover, transistors are the main elements in the circuit whose performance variation must be consider when the design target is compensating the temperature effects. The influence of the temperature variation is studied on the transistors and the building blocks in order to find the most effective approaches to compensate these variations and stabilize the performance of the RF chain at temperatures up to 220 C. A temperature sensor is designed to sense these variations and adjust the characteristics of the circuit components (e.g. bias voltages), accordingly. Further, a new variable gain phase shifter (VGPS) architecture is introduced toward minimizing the temperature impact on its performance in a phased-array transmitter architecture. Finally, a power amplifier as the last stage in a transmitter chain is designed and the variation in its performance with temperature is compensated through the VGPS stage. The transmitter is prototyped to evaluate its performance in practice. Another contribution of this dissertation is to introduce a novel voltage-controlled oscillator (VCO) structure to reduce the phase noise level below state-of-the-art. The noise to phase noise mechanism in the introduced doubly tuned oscillator is studied using linear time-variant (LTV) theory to identify the dominant noise sources and either eliminate or suppress these noise sources by introducing effective mechanism such as impedance scaling. The designed VCO is fabricated and measurement results are carried out that justified the accuracy of the analyses and effectiveness of the introduced design approach. Lastly, we introduce a compact and simple polar transmitter architecture. This type of transmitters was firstly proposed to overcome the serious shortcomings in the IQ transmitters, such as IQ imbalance and carrier leakage. However, there is still several challenges in their design. We introduce a transmitter architecture that operates based on charge to phase translation mechanism in the oscillator. This leads to significantly reduction in the design complexity, die area, and power dissipation. Further, it eliminates a number of serious issues in the design such as sampling rate of the DACs. comprehensive post-layout simulations were also performed to evaluate its performance. / Doctor of Philosophy / To keep up with the ever-growing demand for exchanging information through a radio frequency (RF) wireless network, the specification of the communication hardware (i.e. transmitter and receiver) must be improved as the bottleneck of the system. This has been motivating engineers to introduce new and efficient approaches toward this goal. In this dissertation however, we study three aspects of the circuit design. First, variation in the ambient temperature can significantly degrade the performance of the communication system. Therefore, we study these variations on the performance of the transmitter at high temperature (i.e. above 200 C). Then, the temperature compensation approaches are introduced to minimize the impact of the temperature changes. The effectiveness of the introduced techniques are validated through measurements of the prototyped transmitter. Second, signal generators (i.e. oscillators) are the inseparable blocks of the transmitters. Phase noise is one of the most important specifications of the oscillators that can directly be translated to the quality and data rate of the communication. A new oscillator structure targeting ultra-low phase noise is introduced in the second part of this dissertation. The designed oscillator is fabricated and measured to evaluate its performance. Finally, a new polar transmitter architecture for low power applications is introduced. The transmitter offers design simplicity and compact size compared to other polar transmitter architectures while high performance.

In-phase and quadrature (I/Q) signal generation is often required in modern transceiver architectures, such as direct conversion or low-IF, either for vector modulation and demodulation, negative frequency recovery in direct conversion receivers, or image rejection. If imbalance between the I and Q channels exists, the bit-error-rate (BER) of the transceiver and/or the image rejection ratio (IRR) will quickly deteriorate. Methods for correcting I/Q imbalance are desirable and necessary to improve the performance of quadrature transceiver architectures and modulation schemes. This thesis presents the design and characterization of a monolithic 5-6 GHz Silicon Germanium (SiGe) inductor-capacitor (LC) tank voltage controlled oscillator (VCO) with tunable polyphase outputs. Circuits were designed and fabricated using the Motorola 0.4 ìm CDR1 SiGe BiCMOS process, which has four interconnect metal layers and a thick copper uppermost bump layer for high-quality radio frequency (RF) passives. The VCO design includes full-wave electromagnetic characterization of an electrically symmetric differential inductor and a traditional dual inductor. Differential effective inductance and Q factor are extracted and compared for simulated and measured inductors. At 5.25 GHz, the measured Q factors of the electrically symmetric and dual inductors are 15.4 and 10.4, respectively. The electrically symmetric inductor provides a measured 48% percent improvement in Q factor over the traditional dual inductor. Two VCOs were designed and fabricated; one uses the electrically symmetric inductor in the LC tank circuit while the other uses the dual inductor. Both VCOs are based on an identical cross-coupled, differential pair negative transconductance -GM oscillator topology. Analysis and design considerations of this topology are presented with a particular emphasis on designing for low phase noise and low-power consumption. The fabricated VCO with an electrically symmetric inductor in the tank circuit tunes from 4.19 to 5.45 GHz (26% tuning range) for control voltages from 1.7 to 4.0 V. This circuit consumes 3.81 mA from a 3.3 V supply for the VCO core and 14.1 mA from a 2.5 V supply for the output buffer. The measured phase noise is -115.5 dBc/Hz at a 1 MHz offset and a tank varactor control voltage of 1.0 V. The VCO figure-of-merit (FOM) for the symmetric inductor VCO is -179.2 dBc/Hz, which is within 4 dBc/Hz of the best reported VCO in the 5 GHz frequency regime. The die area including pads for the symmetric inductor VCO is 1 mm x 0.76 mm. In comparison, the dual inductor VCO tunes from 3.50 to 4.58 GHz (27% tuning range) for control voltages from 1.7 to 4.0 V. DC power consumption of this circuit consists of 3.75 mA from a 3.3 V supply for the VCO and 13.3 mA from a 2.5 V supply for the buffer. At 1 MHz from the carrier and a control voltage of 0 V, the dual inductor VCO has a phase noise of -104 dBc/Hz. The advantage of the higher Q symmetric inductor is apparent by comparing the FOM of the two VCO designs at the same varactor control voltage of 0 V. At this tuning voltage, the dual inductor VCO FOM is -166.3 dBc/Hz compared to -175.7 dBc/Hz for the symmetric inductor VCO -- an improvement of about 10 dBc/Hz. The die area including pads for the dual inductor VCO is 1.2 mm x 0.76 mm. In addition to these VCOs, a tunable polyphase filter with integrated input and output buffers was designed and fabricated for a bandwidth of 5.15 to 5.825 GHz. Series tunable capacitors (varactors) provide phase tunability for the quadrature outputs of the polyphase filter. The die area of the tunable polyphase with pads is 920 ìm x 755 ìm. The stand-alone polyphase filter consumes 13.74 mA in the input buffer and 6.29 mA in the two output buffers from a 2.5 V supply. Based on measurements, approximately 15° of I/Q phase imbalance can be tuned out using the fabricated polyphase filter, proving the concept of tunable phase. The output varactor control voltages can be used to achieve a potential ±5° phase flatness bandwidth of 700 MHz. To the author's knowledge, this is the first reported I/Q balance tunable polyphase network. The tunable polyphase filter can be integrated with the VCO designs described above to yield a quadrature VCO with phase tunable outputs. Based on the above designs I/Q tunability can be added to VCO at the expense of about 6 mA. Future work includes testing of a fabricated version of this combined polyphase VCO circuit. / Master of Science

Les travaux présentés dans ce mémoire d'habilitation portent sur l'impact du bruit de fond électrique sur les technologies des composants actifs, les circuits et les systèmes des hautes fréquences. Durant nos 12 dernières années de recherche, nous nous sommes notamment intéressés à des filières émergentes à fort potentiel d'intégration (BiCMOS Silicium-Germanium) ou encore à forte puissance (GaN) : nous avons ainsi développé des modèles électriques (petit signal et fort signal) et en bruit (basse fréquence et haute fréquence) des composants actifs pour identifier les pistes d'améliorations technologiques, pour localiser les défauts structurels ou pour étudier le comportement de ces mêmes défauts après l'application de contraintes simulant un vieillissement accéléré. Sur la base de la connaissance des composants actifs (transistor bipolaire à hétérojonction et transistors à effet de champ), nous avons développé des circuits intégrés MMIC faible bruit à 10 GHz et 20 GHz (amplificateurs et oscillateurs) dont certains se positionnent à l'état de l'art : des comparaisons de topologies ont notamment été réalisées sur différentes versions intégrées d'oscillateurs contrôlés en tension de type MMIC SiGe. Nous proposons également une discussion sur la pertinence des facteurs de mérite usuellement employés. D'autres études sur des atténuateurs programmables MMIC SiGe ont fait l'objet de brevets. La troisième partie, orientée système, aborde l'étude du bruit d'un récepteur : nous traitons ainsi le cas d'un étage de réception affecté par la chaîne d'émission, en proposant différentes parades permettant de limiter les dégradations de son plancher de bruit ; une technique de filtre compact intégré à l'amplificateur faible bruit a ainsi été brevetée. Enfin, le cas d'un système de liaison hertzienne embarqué sur automobile est abordé. Diverses stratégies sont ainsi proposées pour pallier les évènements conduisant à une rupture de la liaison (diversité temporelle, diversité spatiale et diversité de polarisation). Ces études reposent sur une approche mixte de traitement de mesures par des modèles théoriques, et des simulations électromagnétiques.