Dans cette thèse nous nous intéressons à la prédiction de la réussite à l’issue de la formation (réussite à l’examen à l’université, insertion de demandeurs d’emplois accueillis en formation) sur la base de mesures subjectives « à chaud » (satisfaction ou apprentissages subjectifs) et de variables dispositionnelles (sentiment d’efficacité personnelle, locus de contrôle, estime de soi, optimisme et évaluation centrale de soi). Les résultats montrent en rapport avec les modèles d’évaluation de la formation que les mesures subjectives « à chaud » ne sont pas de bons prédicteurs de la réussite à l’issue de la formation ou de l’insertion professionnelle. Par ailleurs, la réussite à l’issue de la formation peut parfois être prédite par les variables dispositionnelles dans la mesure où ces dernières ont des valeurs élevées, dans le cas d’obtention au préalable de bonnes notes de la part des étudiants. En effet, l’effet de prédiction disparait lorsqu’est neutralisé l’impact du niveau académique antérieur de l’étudiant. En accord avec les travaux sur la norme d’internalité, ces variables semblent des indicateurs de situations sociales de réussite préexistantes et non des déterminants directs de la réussite sociale (Dubois, 1987, 2003). Dans la seconde partie de notre thèse, nous proposons par le biais de la théorie de l’engagement d’agir sur le contexte au moyen d’une déclaration de liberté ayant pour objet la présence au cours. Des effets positifs de la déclaration de liberté, par opposition à une déclaration de contrainte, sont observés sur plusieurs résultats collectés en fin de formation (satisfaction, apprentissage subjectif). Au niveau théorique, il semble que les retours d’évaluation fournis par les formateurs pourraient affecter les variables dispositionnelles, dont font état les personnes formées, et ainsi les rendre prédictives de la réussite. Les interactions évaluatives réifieraient ainsi le lien entre variables dispositionnelles et situation de réussite. Par ailleurs le contexte de liberté induit pourrait favoriser une élévation des mesures dispositionnelles et initier les processus d’apprentissage. / This research work adresses the prediction of success after a training scheme (success in university examination, integration of job seekers after a training session) on the basis of 1/ subjective indicators at the end of training: satisfaction or subjective learning and 2/ individuals' variables (self-efficacy, locus of control, self-esteem, optimism and core self-evaluation). Our results show that, compared to training evaluation models, subjective indicators at the end of training do not appear to be good predictors of success. In addition, if individuals' variables are sometimes predictable of success, this seems to be related to the mere fact that they represent high values in students with past good results (the effect of prediction disappears when the effect of the student's past academic level is neutralized). In agreement with studies carried out on Internality Norm, such variables appear to be no more than indicators of previous social success situations, but not direct determinants of social success (Dubois, 1987, 2003). In the second part of our thesis, we propose – via the theory of commitment – to impact on participants' commitment, thanks to a statement of freedom (of choice) as to the attendance to classes. Favorable effects derived from such freedom of choice – as opposed to compulsory attendance - are observed on several results collected at the end of the training (satisfaction, subjective learning). At theoretical level, It seems that trainers' evaluation assessments could affect declared trainees' individual variables, thus making them predictive of success. Evaluation interactions are thus thought to reify the link usually considered between individuals' variables and situations of success. In addition, the context of freedom thus induced might contribute to enhanced individuals' variables as well as promote the mechanisms of learning.

Ces travaux traitent de la réalisation d’un prototype d’interrupteur monolithique bidirectionnel à base de transistor bipolaire. A terme, l’objectif est de développer un interrupteur intelligent à faible perte, complètement intégrable dans l’habitat. Nous nous intéressons d’abord aux composants bidirectionnels existants. Nous présentons ensuite deux transistors bipolaires bidirectionnels. Le premier à base large, de fabrication aisée. Le second, symétrique, latéral, sur substrat SOI, à base fine, verticale, autoprotégée, très novateur. Nous les comparons et optons pour le transistor latéral à base fine, puis discutons les différentes étapes de sa fabrication et montrons qu’elle constitue un véritable challenge. Ensuite, nous détaillons une méthodologie analytique 1D permettant de déterminer les éléments clefs de fabrication de la partie active du transistor. L’étude est validée par des simulations 2D numériques par éléments finis. Nous continuons par une réflexion sur la périphérie du composant et sa métallisation. Nous détaillons les variantes de réalisation envisagées et montrons que ce composant est robuste vis-à-vis des désalignements entre les masques lors de la fabrication. Finalement, nous caractérisons les transistors fabriqués. Initialement le dispositif est parasité par des effets de ségrégation des dopants aux interfaces SiO2 / Si. Nous expliquons qu’il est possible de contrecarrer ces effets, pour finalement valider le concept de transistor bipolaire symétrique latéral sur substrat SOI, à base fine, verticale, autoprotégée. / This study deals with the realization of a prototype of a low losses monolithic bidirectional switch. It is based on a SOI symmetrical and lateral bipolar transistor with a thin, vertical and shielded base. The goal is to produce a switch which can be integrated to smart electronics functions. First, we compare the existing bidirectional solutions. We then introduce two bidirectional bipolar transistors: one with a wide base, easy to realize, and the other one, patented, symmetrical and lateral, using a SOI substrate, with a thin, vertical and shielded base. We compare these two devices and choose the novel and patented lateral bipolar transistor. We then discuss the challenge of its fabrication. We then detail a 1D analytical methodology allowing to define rapidly the key steps of the active area transistor realization. The study is then confirmed by finite element 2D numerical simulations (Sentaurus). Next, we discuss the periphery and metallization of the device. We detail the variant of process introduced. We finally show that this component is robust to masks misaligning during its fabrication. To the end, the transistors are realized and analyzed. We show that, initially, the segregation of dopants at SiO2 / Si interfaces implies a parasiting canal in parallel of the transistor. We then explain how to reduce these parasiting effects, to finally validate the concept of a symmetrical and lateral bipolar transistor on a SOI substrate, with a thin, vertical, shielded base.

Tunnel à effet de champ (TFET) et un nouveau composant MOS à rétroaction que nous avons nommé le Z2-FET.Le Z2-FET est envisagé pour la logique faible consommation et pour les applications mémoire compatibles avecles technologies CMOS avancées. Nous avons étudié de manière systématique des TFETs avec différents oxydesde grille, matériaux et structures de canal, fabriqués sur silicium sur isolant totalement déserté (FDSOI). Lesmesures de bruit à basse fréquence (LFN) sur TFETs montrent la prédominance d'un signal aléatoiretélégraphique (RTS), qui révèle sans ambiguïté le mécanisme d’effet tunnel. Un modèle analytique combinantl’effet tunnel et le transport dans le canal a été développé, montrant un bon accord entre les résultatsexpérimentaux et les simulations.Nous avons conçu et démontré un nouveau dispositif (Z2-FET, pour pente sous le seuil verticale et zéroionisation par impact), qui présente une commutation extrêmement abrupte (moins de 1 mV par décade decourant), avec un rapport ION / IOFF >109, un large effet de hystérésis et un potentiel de miniaturisation jusqu'à 20nm. La simulation TCAD a été utilisée pour confirmer que la commutation électrique du Z2-FET fonctionne parl'intermédiaire de rétroaction entre les flux des électrons et trous et leurs barrières d'injection respectives. LeZ2-FET est idéalement adapté pour des applications mémoire à un transistor. La mémoire DRAM basée sur leZ2-FET montre des performances très bonnes, avec des tensions d'alimentation jusqu'à 1,1 V, des temps derétention jusqu'à 5,5 s et des vitesses d'accès atteignant 1 ns. Une mémoire SRAM utilisant un seul Z²-FET estégalement démontrée sans nécessité de rafraichissement de l’information stockée.Notre travail sur le courant GIDL intervenant dans les MOSFETs de type FDSOI a été combiné avec leTFET afin de proposer une nouvelle structure de TFETs optimisés, basée sur l'amplification bipolaire du couranttunnel. Les simulations de nouveau dispostif à injection tunnel amélioré par effet bipolaire (BET-FET) montrentdes résultats prometteurs, avec des ION supérierus à 4mA/��m et des pentes sous le seuil SS inférieures à 60mV/dec sur plus de sept décades de courant, surpassant tous les TFETs silicium rapportés à ce jour.La thèse se conclut par les directions de recherche futures dans le domaine des dispositifs à pente sous leseuil abrupte. / This thesis is dedicated to studying sharp switching devices, including the tunneling field-effect-transistor(TFET) and a new feedback device we have named the Z2-FET, for low power logic and memory applicationscompatible with modern silicon technology. We have extensively investigated TFETs with various gate oxides,channel materials and structures, fabricated on fully-depleted silicon-on-insulator (FD-SOI) substrates.Low-frequency noise (LFN) measurements were performed on TFETs, showing the dominance of randomtelegraphy signal (RTS) noise, which reveals the tunneling mechanism. An analytical TFET model combiningtunneling and channel transport has been developed, showing agreement with the experimental and simulationresults.We also conceived and demonstrated a new device named the Z2-FET (for zero subthreshold swing andzero impact ionization), which exhibits extremely sharp switching with subthreshold swing SS < 1 mV/dec,ION/IOFF current ratio reaching 109, gate-controlled hysteresis and scalability down to 20 nm. The Z2-FEToperates with feedback between carriers flow and their injection barriers. The Z2-FET is used for one-transistordynamic random access memory (DRAM) with supply voltage down to 1.1 V, retention time up to 5.5 s andaccess speed reaching 1 ns. The static RAM (SRAM) application is also demonstrated without the need ofrefreshing stored data.Following our work on gate-induced drain leakage (GIDL) current in short-channel FD-SOI MOSFETs andon TFET operating mechanisms, we propose a new class of optimized TFETs with enhanced ION, based on thebipolar amplification of the tunneling current. Simulations of the bipolar-enhanced tunneling FET (BET-FET),combining the TFET with a heterojunction bipolar transistor, show promising results, with ION > 4×10-3 A/��mand SS < 60 mV/dec over 7 decades of current, outperforming all silicon-compatible TFETs reported to date.The thesis concludes with future research directions in the sharp-switching device arena.

O objetivo principal deste trabalho é o estudo de transistores UTBOX SOI não auto-alinhados operando como célula de memória de apenas um transistor aproveitando-se do efeito de corpo flutuante (1T-FBRAM single Transistor Floating Body Random Access Memory). A caracterização elétrica dos dispositivos se deu a partir de medidas experimentais estáticas e dinâmicas e ainda, simulações numéricas bidimensionais foram implementadas para confirmar os resultados obtidos. Diferentes métodos de escrita e leitura do dado 1 que também são chamados de métodos de programação do dado 1 são encontrados na literatura, mas com intuito de se melhorar os parâmetros dinâmicos das memórias como o tempo de retenção e a margem de sensibilidade e ainda, permitir um maior escalamento dos dispositivos totalmente depletados, o método de programação utilizado neste trabalho será o BJT (Bipolar Junction Transistor). Uma das maiores preocupações para a aplicação de células 1T-DRAMs nas gerações tecnológicas futuras é o tempo de retenção que diminui juntamente com a redução do comprimento de canal do transistor. Com o intuito de solucionar este problema ou ao menos retardá-lo, é apresentando pela primeira vez um estudo sobre a dependência do tempo de retenção e da margem de sensibilidade em função do comprimento de canal, onde se observou que esses parâmetros dinâmicos podem ser otimizados através da polarização do substrato e mantidos constantes para comprimentos de canal maiores que 50 no caso dos dispositivos não auto-alinhados e 80 nos dispositivos de referência. Entretanto, observou-se também que existe um comprimento de canal mínimo que é dependente do tipo de junção (30 no caso dos dispositivos não auto-alinhados e 50 nos dispositivos de referência) de modo que para comprimentos de canal abaixo desses valores críticos não há mais espaço para otimização dos parâmetros, degradando assim o desempenho da célula de memória. O mecanismo de degradação dos parâmetros dinâmicos de memória foi identificado e atribuído à amplificação da corrente de GIDL (Gate Induced Drain Leakage) pelo transistor bipolar parasitário de base estreita durante a leitura e o tempo de repouso do dado 0. A presença desse efeito foi confirmada através de simulações numéricas bidimensionais dos transistores quando uma alta taxa de geração de portadores surgiu bem próxima das junções de fonte e dreno somente quando o modelo de tunelamento banda-a-banda (bbt.kane) foi considerado. Comparando o comportamento dos dispositivos não auto-alinhados com os dispositivos de referência tanto nos principais parâmetros elétricos (tensão de limiar, inclinação de sublimiar, ganho intrínseco de tensão) como em aplicações de memória (tempo de retenção, margem de sensibilidade, janela de leitura), constatou-se que a estrutura não auto-alinhada apresenta melhor desempenho, uma vez que alcança maior velocidade de chaveamento devido a menor inclinação de sublimiar; menor influência das linhas de campo elétrico nas cargas do canal, menor variação da tensão de limiar, até mesmo com a variação da temperatura. Além disso, constatou-se que os dispositivos não auto-alinhados são mais escaláveis do que os dispositivos de referência, pois são menos susceptíveis à corrente de GIDL, apresentando menor campo elétrico e taxa de geração próximos das junções de fonte e dreno que os dispositivos de referência, alcançando então um tempo de retenção de aproximadamente 6 e margem de sensibilidade de aproximadamente 71 A/m. Segundo as especificações da International Technology Roadmap for Semicondutor de 2011, o valor do tempo de retenção para as memórias DRAM convencionais existentes no mercado de semicondutores é de aproximadamente 64. Com o intuito de aumentar o tempo de retenção das 1T-DRAMs a valores próximos à 64 recomenda-se então o uso da tecnologia não auto-alinhada e também a substituição do silício por materiais com maior banda proibida (band-gap), como exemplo o arseneto de gálio e o silício-carbono, dificultando assim o tunelamento dos elétrons e, consequentemente, diminuindo o GIDL. / The main topic of this work is the study of extensionless UTBOX SOI transistors, also called underlapped devices, applied as a single transistor floating body RAM (1T-FBRAM single transistor floating body access memory). The electrical characterization of the devices was performed through static and dynamic experimental data and two dimensional simulations were implemented to confirm the obtained results. In the literature, different methods to write and read the data 1 can be found but in order to improve the dynamic parameters of the memories, as retention time and sense margin and still allows the scaling of fully depleted devices, the BJT (Bipolar Junction Transistor) method is used in this work. One of the biggest issues to meet the specifications for future generations of 1T-DRAM cells is the retention time that scales together with the channel length. In order to overcome this issue or at least slow it down, in this work, we present for the first time, a study about the retention time and sense margin dependence of the channel length where it was possible to observe that these dynamic parameters can be optimized through the back gate bias and kept constant for channel lengths higher than 50 nm for extensionless devices and 80 nm for standard ones. However, it was also observed that there is a minimal channel length which depends of the source/drain junctions, i.e. 30 nm for extensionless and 50 nm for standard devices in the sense that for shorter channel lengths than these ones, there is no room for optimization degrading the performance of the memory cell. The mechanism behind the dynamic parameters degradation was identified and attributed to the GIDL current amplification by the lateral bipolar transistor with narrow base. Simulations confirmed this effect where higher generation rates near the junctions were presented only when the band-toband- tunneling adjustment was considered (bbt.kane model). Comparing the performance of standard and extensionless devices in both digital and analog electrical parameters and also in memory applications, it was found that extensionless devices present better performance since they reach faster switching which means lower subthreshold slope; less influence of the electrical field in the channel charges; less variation of the threshold voltage even increasing the temperature. Furthermore, it was seen that the gate length can be further scaled using underlap junctions since these devices are less susceptible to the GIDL current, presenting less electric field and generation rate near the source/drain junctions and reach a retention time of around 4 ms and sense margin of 71A/m. According to the International Technology Roadmap for Semiconductor of 2011, the retention time for the existing DRAM is around 64 ms. In order to increase the retention time of the 1T-DRAMs to values close to 64 ms it is recommended the use of extensionless devices and also the substitution of silicon by materials with higher band gap, i.e., gallium arsenide and siliconcarbon, which makes difficult the electron tunneling therefore, decreasing the GIDL.

L’objet de ce travail est d’éclairer l’esthétique et l’éthique de la poétique de Francis Ponge à partir de la notion de Nature. La première partie étudie la notion de Nature chez Ponge en tant que monde extérieur et son matérialisme qui, fortement influencé par le matérialisme antique, est caractérisé par l’antimétaphysique. Cette partie met également en relief le rapport étroit entre sa pensée matérialiste et la pensée immanente spinoziste, résumée dans l’expression de « Dieu ou la Nature ». Les aspects immanents des choses dans ses œuvres peuvent être mieux saisis, en effet, à l’aide de la notion d’« immanence » spinoziste. La deuxième partie explore, quant à elle, la relation entre la Nature et la littérature et le développement d’un nouveau lyrisme matérialiste chez Ponge. Pour lui, la littérature se naturalise et la Nature se littérarise. Son approbation de la Nature se traduit par sa contresignature apposée aux choses.Son nouveau lyrisme matérialiste, qui s’oppose au lyrisme traditionnel, se caractérise autour de notions telles que la vibration, l’aspiration, ou la « réson ». La troisième partie, enfin, examine le nouvel humanisme de Ponge ainsi que son éthique.La relation entre la Nature et l’homme s’articulera autour de thèmes éthiques essentiels comme l’altérité, le nouvel humanisme et le salut de l’homme. Son éthique consiste à vivre heureux. Nous l’aborderons à travers différents thèmes tels que la sagesse antique, l’harmonie du « non-soi » et du « soi », l’éthique de la joie, le hasard et la liberté. / The purpose of this study is to examine the aesthetics and the ethics of Francis Ponge’s poetry through the notion of Nature. The first part examines the concept of Nature in Ponge as the outside world and his materialism which, heavily influenced by ancient materialism, is characterized by the anti-metaphysical. This part also explore the close relationship between his idea and Spinoza’s immanent idea, summarized in the expression of "God, or Nature". The immanent aspects of things in his work can be fully understood with the help of the concept of "immanence" of Spinoza. The second part examines the relationship between Nature and literature and the development of Ponge’s new materialist lyricism. For him, literature becomes naturalized and nature becomes literarized. The approval of nature is reflected in his countersignature for things. His new materialist lyricism, contrasted with the traditional lyricism, is characterized by notions such as vibration, aspiration, "réson". The third part will focus on the new humanism and the ethics of Ponge. The relationship between Nature and man will be treated primarily on certain essential themes of ethics such as otherness, the new humanism and the salvation of man. His ethics is to live à happy life. Various topics, such as ancient wisdom, the harmony of the "non-self" and the "self", the ethics of joy, chance and freedom, will be discussed.

Les cinq études détaillées au cours de cette thèse interrogent divers aspects de la théorie de l’esprit, de la conscience de soi ainsi que du lien (multiple ou unique) qui unit ces deux capacités sociocognitives si particulières. Les deux premières études mettent en évidence différentes variables qui peuvent – ou non- influencer l’attribution d’intention et de fausse croyance à autrui. La troisième étude porte plus précisément sur les différents composants de la conscience de soi et sur leur trajectoire développementale. La quatrième étude interroge le lien développemental entre la théorie de l’esprit et la conscience de soi, alors que la dernière étude questionne la présence de ce lien chez les chimpanzés (Pan Troglodytes). Nous démontrerons, tout au long de cette thèse, que la théorie de l’esprit et la conscience de soi sont composées de différents éléments et que leur acquisition est graduelle. / Doctorat en Sciences Psychologiques et de l'éducation / info:eu-repo/semantics/nonPublished

Silicon photonics as a one of the most promising photonic integration technologies has attracted many attentions in recent years. The major feature of this technology is its compatibility with complementary metal-oxide semiconductor (CMOS) processes which makes it possible to integrate optical and electronic devices in a same chip and reduce the cost significantly. Another reason of using silicon photonics is the high index contrast between the silicon core and silicon dioxide cladding which ensures the high density integration of photonic devices on a single chip. Monolithic integration with electronic and optical circuits makes silicon photonics technology suitable for numerous applications. One example is microwave photonics (MWP). MWP is an area that studies the interaction between microwave and optical signal for the generation, processing, control and distribution of microwave signals by means of photonics. Silicon photonics offers a reduction in footprint, losses, packaging cost and power dissipation in MWP systems. This research in this thesis is focused on the design and fabrication of the silicon photonic devices for MWP signal processing and generation. Four MWP systems based on silicon photonic devices are proposed and experimentally demonstrated. 1) A single pass-band frequency-tunable MWP filter based on phase-modulation to intensity-modulation conversion in an optically pumped silicon-on-insulator (SOI) microring resonator (MRR) is designed and experimentally demonstrated. In the proposed filter, a phase-modulated optical signal is filtered by the SOI MRR, to have one first-order sideband suppressed by the MRR notch. The phase-modulated optical signal is converted to an intensity-modulated single-sideband (SSB) signal and detected at a photodetector (PD). The entire operation is equivalent to a single pass-band filter. The frequency tunability is achieved by tuning the resonance wavelength of the MRR, which is realized by optically pumping the MRR. A single pass-band MWP filter with a tunable center frequency from 16 to 23 GHz is experimentally demonstrated. 2) A broadband optically tunable MWP phase shifter with a tunable phase shift using three cascaded SOI MRRs that are optically pumped is designed and experimentally demonstrated. A microwave signal to be phase shifted is applied to an optical single-sideband (OSSB) modulator to generate an optical carrier and an optical sideband. The phase shift is introduced to the optical carrier by placing the optical carrier within the bandwidth of one resonance of the three cascaded MRRs. The experimental results show that by optically pumping the cascaded MRRs, a broadband MWP phase shifter with a bandwidth of 7 GHz with a tunable phase shift covering the entire 360o phase shift range is achieved. 3) A multi tap MWP filter with positive and negative coefficients using a silicon ring resonator modulator (RRM) is proposed and experimentally demonstrated. The RRM is designed and fabricated to operate based on the carrier depletion effect. The positive and negative coefficients are obtained by using opposite slopes of the modulation transmission response of the RRM. Two filter responses with two and three taps are experimentally demonstrated, showing the proof-of-principle for frequencies up to 18 GHz. 4) An approach to generate microwave signal based on enhanced four wave mixing (FWM) in an active silicon waveguide (SiWG) is studied. This SiWG is designed and fabricated, and the use of the active SiWG for MWP frequency multiplication to generate a frequency-sextupled millimeter-wave signal is experimentally demonstrated. Thanks to a reverse-biased p-n junction across the SiWG, the conversion efficiency of the FWM is improved, which leads to the improvement of the microwave frequency multiplication efficiency.

En ce début du XXIème siècle, un nombre d’auteurs sans cesse plus important développe un véritable enthousiasme pour des thématiques féminines. Plus précisément, il s’agit pour eux de mettre en exergue la quête identitaire des femmes dans notre société. Cette littérature révèle une omniprésence du corps et de la sexualité en lien étroit avec la société et les schémas culturels imposés tenant ainsi un discours novateur sur les femmes. Le but de cette recherche est de montrer comment un discours littéraire, en reprenant les discours socioculturels, féministes et psychanalystes du moment, conçoit la question de la femme et quelle représentation de la femme il produit. Face à cette réflexion sur la question de la femme et son identité, cette thèse centre son étude sur les romans de trois auteurs, Virginie Despentes, écrivain français, Lucía Etxebarria, écrivain espagnol et Maïssa Bey, écrivain algérien francophone. L’être femme est représenté dans un rapport avec la violence masculine mais aussi avec sa propre violence, dans son rapport au corps et à la sexualité, par des relations humaines conflictuelles ainsi que par une aliénation sociale et culturelle. Le personnage féminin est un personnage seul, enfermé dans une identité dans laquelle il ne se reconnaît plus et qu’il rejette. La quête de soi et de la reconnaissance de soi laisse apparaître leurs aspirations, en contradictions avec leurs attributions. A la fin de chaque roman, l’individualisation de la femme est envisagée par la reprise de parole. La reconstruction de soi ne peut être permise que par la maîtrise de la parole sur soi, et la quête d’individualisation doit se poursuivre / In our early 21th century, an increasingly number of writers gets a real enthusiasm for woman-related themes. More precisely, their purpose is to underline the identity quest of women in our society. This kind of literature uncovers a constant involvement of body and sexuality closely linked to society and to cultural schemes that society imposes - thus leading these authors to hold an innovative discourse about women. Our research aims to show how a literary discourse, drawing from actual sociocultural, feminist and psychoanalytic discourses, conceives the Woman issue and which representation of woman it can create. At the hands of this reflection about the Woman issue and her identity, the study focuses on three female authors’ novels, Virginie Despentes, a french writer, Lucia Extebarría, a spanish writer and Maïssa Bey, an algerian French-speaking writer. The woman being is portrayed in her relations with male violence but also with her own violence linked to her relation to body and sexuality, and through human struggles and a social and cultural alienation. The female character is lonely, confined to an identity in which she does not recognize herself anymore and that she rejects. The quest for self-knowledge and for self-recognition lets its longings emerge, in contradiction with their remit. In the end of each novel, woman’s individualization is imaged through a takeover of speech. Self-reconstruction can only be possible thanks to a control of speech about oneself and the individuation quest has to keep going

Suffisante pour exécuter les algorithmes à la cadence de ces capteurs d’images performants, tout en gardant une faible consommation d’énergie. Les systèmes monoprocesseur n’arrivent plus à satisfaire les exigences de ce domaine. Ainsi, grâce aux avancées technologiques et en s’appuyant sur de précédents travaux sur les machines parallèles, les systèmes multiprocesseurs sur puce (MPSoC) représentent une solution intéressante et prometteuse. Dans de précédents travaux à cette thèse, la cible technologique pour développer de tels systèmes était les FPGA. Or les résultats ont montré les limites de cette cible en terme de ressource matérielles et en terme de performance (vitesse notamment). Ce constat nous amène à changer de cible c’est-à-dire à passer sur cible ASIC nécessitant ainsi de retravailler profondément l’architecture et les IPs qui existaient autour de la méthode existante (appelée HNCP, pour Homogeneous Network of Communicating Processors). Afin de bénéficier de la performance offerte par la cible ASIC, les systèmes multiprocesseurs proposés s’appuient sur la flexibilité de son architecture. Combinés à des squelettes de parallélisation facilitant la programmabilité de l’architecture, les circuits proposés permettent d’offrir des systèmes supportant le portage en temps réels de différentes classes d’algorithme de traitement d’images. Le résultat de ce travail a abouti à la fabrication d’un circuit intégré à base d’un seul processeur et de ses périphériques en technologie ST CMOS 65nm dont la surface est d’environ 1 mm² et à la définition de 2 architectures multiprocesseurs flexibles basées sur le concept des squelettes de parallélisation (une architecture de 16 coeurs de processeur en technologie ST CMOS 65 nm et une deuxième architecture de 64 coeurs de processeur en technologie ST CMOS FD-SOI 28 nm). / Smart sensors today require processing components with sufficient power to run algorithms at the rate of these high-performance image sensors, while maintaining low power consumption. Monoprocessor systems are no longer able to meet the requirements of this field. Thus, thanks to technological advances and based on previous works on parallel computers, multiprocessor systems on chip (MPSoC) represent an interesting and promising solution. Previous works around this thesis have used FPGA as technological target. However, results have shown the limits of this target in terms of hardware resources and in terms of performance (speed in particular). This observation leads us to change the target from FPGA to ASIC. This migration requires deep rework at the architecture level. Particularly, existing IPs around the method (called HNCP for Homogeneous Network of Communicating Processors) have to be revisited. To take advantage of the performance offered by the ASIC target, proposed multiprocessor systems are based on the flexibility of its architecture. Combined with parallel skeletons that ease programmability of the architecture, the proposed circuits allow to offer systems that support various real-time image processing algorithms. This work has led to the fabrication of an integrated circuit based on a single processor and its peripheral using ST CMOS 65nm technology with an area around 1 mm². Moreover, two flexible multiprocessor architectures based on the concept of parallel skeletons have been proposed (a 16 cores 65 nm CMOS multiprocessors and a 64 cores 28 nm FD-SOI CMOS multiprocessors).

L’intégration photonique permet de réduire la taille et la consommation d’énergie des systèmes de communication par fibre optique par rapport aux systèmes assemblés à partir de composants unitaires. Cette technologie a récemment suscité un grand intérêt avec les progrès de l’intégration sur InP et le développement de la photonique sur silicium. Cette dernière challenge la plate-forme d’intégration sur InP car des composants à hautes performances et faibles coûts peuvent être fabriqués dans des fonderies originellement développées pour la microélectronique. Les lasers sont l'une des pièces maitresses des émetteurs-récepteurs pour les communications optiques. Leur intégration sur la plateforme silicium permet de développer des émetteurs-récepteurs comprenant les fonctions critiques d’émission de lumière, de modulation et de détection sur une même puce. L’intégration de matériaux III-V par collage moléculaire sur plaque silicium permet de produire de grands volumes : plusieurs dizaines voire centaines de composants sont réalisés par wafer. Dans cette thèse, j’ai étudié théoriquement et expérimentalement les propriétés des lasers accordables basés sur des résonateurs en anneau en silicium, des lasers à rétroaction distribuée modulés directement et des lasers à haut facteur de qualité qui présentent un faible bruit de phase et d’intensité. / Photonic integration reduces the size and energy consumption of fiber optic communication systems compared to systems assembled from discrete components. This technology has recently attracted a great interest with the progress of integration on InP and the development of silicon photonics. The latter challenges the integration platform on InP as high-performance and low-cost components can be manufactured in foundries originally developed for microelectronics. Lasers are one of the main parts of transceivers for optical communications. With their integration on the silicon platform, transceivers that include the critical functions of light emission, modulation and detection on the same chip can be made. In the heterogeneous integration platform, components are manufactured in high volumes: several tens or even hundreds of components are produced per wafer. In this thesis, I studied theoretically and experimentally the properties of tunable lasers based on silicon ring resonators, directly modulated distributed feedback lasers and low noise high-quality factor lasers