Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal

Ce sujet de thèse a pour objectif principal la conception de protection contre les décharges électrostatiques (ESD) en technologie silicium avancée sur isolant film mince (FDSOI) avec la compatibilité substrat massif. Ceci suppose une caractérisation ESD des dispositifs élémentaires déjà existants et une conception complète de nouveaux dispositifs sur technologie FDSOI. Ces caractérisations se feront, soit en collaboration avec les équipes de caractérisation ESD présents à STMicroelectronics-Crolles, soit directement par le doctorant grâce au banc de test ESD présent dans le laboratoire pour les développements plus en amont si besoin. La caractérisation fine des mécanismes physiques et des performances des composants sera menée à IMEP qui dispose des équipements adéquats (bancs de mesures en basse et haute température, bruit, pompage de charge, etc) et d’une compétence scientifique incontournable. Il sera ensuite nécessaire d’effectuer des choix de stratégies de protection ESD en fonction des applications et des circuits visés par les équipes de STMicroelectronics. On gardera à l’esprit la notion de fiabilité dès la conception de la protection. Une des stratégies envisagée pour la réalisation de protections ESD compatibles avec des films ultra-minces est l’intégration de ces dispositifs sur substrats hybrides. En effet, il a été démontré chez STMicroelectronics en partenariat avec le LETI qu’il était possible de co-intégrer à partir d’un substrat SOI des dispositifs FDSOI ainsi que des dispositifs bulk. Ceci est rendu possible au moyen d’un réticule supplémentaire qui permet de venir retirer le film de silicium et l’oxyde enterré aux endroits voulus. Ainsi la protection ESD est similaire à celle réalisée sur silicium massif mais avec des implantations compatibles avec des dispositifs à film mince. Les dispositifs sont donc sensiblement différents de ceux réalisés sur bulk et nécessitent une caractérisation approfondie afin de les optimiser au mieux. Une approche ambitieuse vise à concevoir des composants SOI inédits, utilisables pour la protection ESD. Ce volet du travail sera en autre effectué sous la responsabilité de l’IMEP qui a récemment inventé et publié plusieurs types de transistors révolutionnaires : Z2-FET, TFET et BET-FET [12-14].Les études se feront sur des dispositifs silicium sur isolant issus des technologies de fabrication STMicroelectronics. Pour ce faire, il sera nécessaire d’appréhender les techniques de fabrication. Dans ce cadre, une simulation des processus de fabrication est envisagée sous la chaîne d’outil ISE-TCAD en C20nm et technologies futures. Tout d’abord ceci permettra d’embrasser l’ensemble des possibilités inhérentes à la création de nouveaux composants dans la technologie considérée et ensuite cette étude préliminaire fournira des structures de simulation pour les configurations ESD. Parallèlement, les outils TCAD de simulation physique du semi-conducteur à gap indirect type silicium seront mis à profit pour étudier plus précisément le comportement du composant élémentaire de protection ESD. Ces éléments peuvent être par exemple de type : diode, ggNMOS, Tr BIMOS, SCR ou SCR, T2, Beta-matrice, PPP… La synergie avec l’IMEP est essentielle pour l’identification et l’analyse des mécanismes physiques gouvernant le fonctionnement des dispositifs. Notamment, l’objectif principal est d’intégrer la protection ESD dans son application finale et d’évaluer son efficacité et son dimensionnement par l’intermédiaire de paramètres géométriques par exemple. Il sera également possible de réaliser des simulations mixtes afin de mieux tenir compte des effets 3D de la structure (effet de coins, dépolarisation de substrat) et de connaître l’influence des circuits de déclenchement associés à cette protection. L’optimisation de l’implantation de la protection ESD sera alors envisageable au regard des résultats de simulation. On se place ici dans le cadre d’une démarche de Co-Design de protection ESD. / "The thesis main objective is the design of protection againstelectrostatic discharge (ESD), for deep submicron (DSM)state-of-the-art fully depleted silicon-on-insulator technology (FDSOI).This requires the ESD characterization of existing elementary devicesand design of new FDSOI devices. The detailed characterization of thephysical mechanisms and device performance will be conducted at IMEPwhich has adequate facilities and scientific competence in this field.It will then be necessary to make choices for ESD protectionstrategies based on circuit applications by STMicroelectronics. Anambitious approach aims to develop novel SOI components used for ESDprotection. This part of the work will be performed under theresponsibility of IMEP as it has has recently invented and publishedseveral types of revolutionary transistors Z 2-FET, TFET andBET-FET. It will be necessary to understand the fabrication processtechnology of STMicroelectronics. In this framework, 3D simulation ofthe technology will be performed on TCAD software for 28nm FDSOI andfuture technologies. Physical simulation, with TCAD tools of thesemiconductor will be used to study more precisely the behavior of theelementary devices of ESD protection. Collaboration with the IMEP isessential for the identification and analysis of the physicalmechanisms governing device operation.In particular, the main objective is to integrate ESD protection andevaluate its effectiveness and design. It will also be possible toperform mixed-mode simulation to better analyse the effects of the 3Dstructure (corner effects, depolarization of substrate) and evaluatethe influence of trigger circuits associated with this protection.Optimizing the implementation of ESD protection will then be possible.Having studied from a theoretical point of view and numericalsimulation, ESD protection cells and trigger circuits associated withthe ESD protection strategy, qualification on silicon will be applied.This will be done by a test vehicle in the chosen SOI technology, andelectrical characterization of the structures and protection networkswill follow. Finally, the ESD performance will be analyzed to provideoptimization of the design and the choice of ESD protection strategybased on targeted applications."

Ce travail présente les principaux résultats obtenus avec une large gamme de dispositifs SOI avancés, candidats très prometteurs pour les futurs générations de transistors MOSFETs. Leurs propriétés électriques ont été analysées par des mesures systématiques, agrémentées par des modèles analytiques et/ou des simulations numériques. Nous avons également proposé une utilisation originale de dispositifs FinFETs fabriqués sur ONO enterré en fonctionnalisant le ONO à des fins d'application mémoire non volatile, volatile et unifiées. Après une introduction sur l'état de l'art des dispositifs avancés en technologie SOI, le deuxième chapitre a été consacré à la caractérisation détaillée des propriétés de dispositifs SOI planaires ultra- mince (épaisseur en dessous de 7 nm) et multi-grille. Nous avons montré l’excellent contrôle électrostatique par la grille dans les transistors très courts ainsi que des effets intéressants de transport et de couplage. Une approche similaire a été utilisée pour étudier et comparer des dispositifs FinFETs à double grille et triple grille. Nous avons démontré que la configuration FinFET double grille améliore le couplage avec la grille arrière, phénomène important pour des applications à tension de seuil multiple. Nous avons proposé des modèles originaux expliquant l'effet de couplage 3D et le comportement de la mobilité dans des TFTs nanocristallin ZnO. Nos résultats ont souligné les similitudes et les différences entre les transistors SOI et à base de ZnO. Des mesures à basse température et de nouvelles méthodes d'extraction ont permis d'établir que la mobilité dans le ZnO et la qualité de l'interface ZnO/SiO2 sont remarquables. Cet état de fait ouvre des perspectives intéressantes pour l'utilisation de ce type de matériaux aux applications innovantes de l'électronique flexible. Dans le troisième chapitre, nous nous sommes concentrés sur le comportement de la mobilité dans les dispositifs SOI planaires et FinFET en effectuant des mesures de magnétorésistance à basse température. Nous avons mis en évidence expérimentalement un comportement de mobilité inhabituel (multi-branche) obtenu lorsque deux ou plusieurs canaux coexistent et interagissent. Un autre résultat original concerne l’existence et l’interprétation de la magnétorésistance géométrique dans les FinFETs.L'utilisation de FinFETs fabriqués sur ONO enterré en tant que mémoire non volatile flash a été proposée dans le quatrième chapitre. Deux mécanismes d'injection de charge ont été étudiés systématiquement. En plus de la démonstration de la pertinence de ce type mémoire en termes de performances (rétention, marge de détection), nous avons mis en évidence un comportement inattendu : l’amélioration de la marge de détection pour des dispositifs à canaux courts. Notre concept innovant de FinFlash sur ONO enterré présente plusieurs avantages: (i) opération double-bit et (ii) séparation de la grille de stockage et de l'interface de lecture augmentant la fiabilité et autorisant une miniaturisation plus poussée que des Finflash conventionnels avec grille ONO.Dans le dernier chapitre, nous avons exploré le concept de mémoire unifiée, en combinant les opérations non volatiles et 1T-DRAM par le biais des FinFETs sur ONO enterré. Comme escompté pour les mémoires dites unifiées, le courant transitoire en mode 1T-DRAM dépend des charges non volatiles stockées dans le ONO. D'autre part, nous avons montré que les charges piégées dans le nitrure ne sont pas perturbées par les opérations de programmation et lecture de la 1T-DRAM. Les performances de cette mémoire unifiée multi-bits sont prometteuses et pourront être considérablement améliorées par optimisation technologique de ce dispositif. / The evolution of electronic systems and portable devices requires innovation in both circuit design and transistor architecture. During last fifty years, the main issue in MOS transistor has been the gate length scaling down. The reduction of power consumption together with the co-integration of different functions is a more recent avenue. In bulk-Si planar technology, device shrinking seems to arrive at the end due to the multiplication of parasitic effects. The relay has been taken by novel SOI-like device architectures. In this perspective, this manuscript presents the main achievements of our work obtained with a variety of advanced fully depleted SOI MOSFETs, which are very promising candidates for next generation MOSFETs. Their electrical properties have been analyzed by systematic measurements and clarified by analytical models and/or simulations. Ultimately, appropriate applications have been proposed based on their beneficial features.In the first chapter, we briefly addressed the short-channel effects and the diverse technologies to improve device performance. The second chapter was dedicated to the detailed characterization and interesting properties of SOI devices. We have demonstrated excellent gate control and high performance in ultra-thin FD SOI MOSFET. The SCEs are efficiently suppressed by decreasing the body thickness below 7 nm. We have investigated the transport and electrostatic properties as well as the coupling mechanisms. The strong impact of body thickness and temperature range has been outlined. A similar approach was used to investigate and compare vertical double-gate and triple-gate FinFETs. DG FinFETs show enhanced coupling to back-gate bias which is applicable and suitable for dynamic threshold voltage tuning. We have proposed original models explaining the 3D coupling effect in FinFETs and the mobility behavior in ZnO TFTs. Our results pointed on the similarities and differences in SOI and ZnO transistors. According to our low-temperature measurements and new promoted extraction methods, the mobility in ZnO and the quality of ZnO/SiO2 interface are respectable, enabling innovating applications in flexible, transparent and power electronics. In the third chapter, we focused on the mobility behavior in planar SOI and FinFET devices by performing low-temperature magnetoresistance measurements. Unusual mobility curve with multi-branch aspect were obtained when two or more channels coexist and interplay. Another original result in the existence of the geometrical magnetoresistance in triple-gate and even double-gate FinFETs.The operation of a flash memory in FinFETs with ONO buried layer was explored in the forth chapter. Two charge injection mechanisms were proposed and systematically investigated. We have discussed the role of device geometry and temperature. Our novel ONO FinFlash concept has several distinct advantages: double-bit operation, separation of storage medium and reading interface, reliability and scalability. In the final chapter, we explored the avenue of unified memory, by combining nonvolatile and 1T-DRAM operations in a single transistor. The key result is that the transient current, relevant for 1T-DRAM operation, depends on the nonvolatile charges stored in the nitride buried layer. On the other hand, the trapped charges are not disturbed by the 1T-DRAM operation. Our experimental data offers the proof-of-concept for such advanced memory. The performance of the unified/multi-bit memory is already decent but will greatly improve in the coming years by processing dedicated devices.

Este trabalho apresenta o estudo do comportamento da mobilidade de portadores em transistores SOI nMOS e pMOS avançados planares e de porta tripla através de simulações tridimensionais e resultados experimentais. Devido à sua estrutura física, os transistores de porta tripla apresentam duas mobilidades, uma referente ao canal de condução na porta superior (orientação cristalográfica ) e uma referente ao canal de condução das portas laterais (orientação cristalográfica ). Inicialmente foi feito um estudo comparativo dos métodos de extração da mobilidade através de simulações numéricas tridimensionais dos dispositivos de porta tripla, tendo como objetivo analisar o comportamento dos diferentes métodos de extração da mobilidade efetiva de portadores e separação das mobilidades da porta superior e laterais, para fazer a escolha dos métodos mais adequados para aplicação nos resultados experimentais. De modo geral todos os métodos estudados sofrem maior influência com a redução do comprimento de canal devido aos efeitos da resistência série e de canal curto. Dentre os métodos estudados o que apresenta maior influência com a redução do comprimento de canal é o por gm,máx que apresentou maiores erros. E o método por Y-function apresentou o melhor comportamento com a redução do comprimento de canal, seguido pelo método Split C-V. Para os dispositivos com comprimento de canal acima de 0,5micro metros o maior erro encontrado foi de 13% para os métodos McLarty e Y-function. Neste caso os métodos por gm,máx e Split C-V apresentaram melhores resultados. Com relação à largura de canal os métodos por gm,máx e Split C-V tiveram os melhores resultados com a utilização de dispositivos de porta tripla. Foi observado que para dispositivos com Wfin maior que 0,7 micro metros os maiores erros encontrados foram de 11,2 % para o método Y-function e 10% para o método por gm,máx. No entanto, para dispositivos com Wfin menores que 0,7 micro metros os métodos Y-function e McLarty apresentaram os piores resultados chegando a quase 50% de erro para o dispositivo mais estreito (Wfin = 50nm). Quanto aos métodos de separação das mobilidades todos os métodos estudados apresentaram bons resultados e se mostraram eficientes mostrando um erro máximo de 11,3%. O que os diferencia é o grau de dificuldade de aplicação. Posteriormente foram realizadas medidas experimentais a fim de possibilitar o entendimento dos fenômenos físicos relacionados à mobilidade de portadores. Primeiramente foram analisados os dispositivos de porta tripla em temperatura ambiente e em baixa temperatura para dispositivos nMOS e pMOS. O estudo foi feito em dispositivos com diferentes comprimentos e larguras de canal a fim de analisar os efeitos das dimensões nesta tecnologia. Em seguida são apresentados os resultados para dispositivos SOI avançados planares em temperatura ambiente com variação da largura de canal e com aplicação de tensão no substrato, com objetivo de analisar o comportamento da mobilidade na primeira interface (óxido de porta/canal) e na segunda interface (óxido enterrado/canal). Esse estudo foi realizado com a aplicação de dois diferentes métodos de extração da mobilidade. Por fim foi feito um estudo de um novo método para extração da mobilidade de portadores chamado de magnetoresistência que consiste na aplicação de um campo magnético perpendicular ao fluxo de corrente do transistor. O uso do campo magnético altera a resistividade do canal, de onde é possível extrair a mobilidade. Foram apresentados os resultados com a utilização deste método para os dispositivos de porta tripla tipo nMOS com variação do comprimento de canal (90 a 910 nm) e da temperatura (200K a 77K). / This work presents a study of the carrier mobility behavior in planar and triple gate advanced SOI nMOS and pMOS transistors through three-dimensional simulations and experimental results. Due to its physical structure, the triple gate transistors presents two mobilities, one referring to the conduction channel on the top gate (crystallographic orientation ) and one referring to the conduction channel on the lateral gates (crystallographic orientation ). Initially, a comparative study of the mobility extraction methods through three-dimensional numerical simulations of the triple gate devices was made, with the purpose to analyze the behavior of different effective carrier mobility and separation of top and lateral gates mobilities extraction methods, to make the choice of the suitable methods for application in the experimental results. From a general way, all the studied methods suffer higher influence with channel length reduction due to short channel and the series resistance effects. Among the studied methods, the method by gm,max presents the higher influence with the channel length reduction that shows the bigger errors. The Y-function method presents the best behavior with the channel length reduction, followed by Split C-V method. For the devices with channel length above 0.5 mirco meters the highest error founded was 13% for McLarty and Y-function methods. In this case the gm,max and Split C-V methods presented the better results. With regard to the channel width the Split C-V and gm,max methods presented the better results with the use of triple gate devices. It was observed that for devices with Wfin higher than 0.7 mirco meters the highest errors founded were 11.2% for the Y-function method and 10% for gm,max method. Nevertheless, for devices with Wfin smaller than 0.7 micro meters the Yfunction and McLarty methods presented the worst results arriving almost 50% of error for the narrowest device (Wfin = 50nm). With regard to mobilities separation methods all the studied methods presented good results and had shown efficient showing a maximum error of 11.3%. The difference between them is the application difficulty level. After that, experimental measures were made in order to make possible the understanding of physical phenomena related to carrier mobility. Firstly, it was analyzed the triple gate devices at room and low temperatures for nMOS and pMOS devices. The study was done in devices with different channel lengths and widths in order to analyze the dimensions effects in this technology. After that it was present the results for planar advanced SOI devices at room temperature with variation of channel width and with the application of back gate voltage, with the purpose to analyze the behavior of the mobility in the first interface (gate oxide/channel) and second interface (buried oxide/channel). This study was done with the application of two different mobility extraction methods. Finally a study of a new mobility extraction method called magnetoresistance was made; this method consists in a perpendicular magnetic field application to transistor current flow. The uses of magnetic field change the channel resistivity, where it is possible to extract the mobility. It was presented results with the use of this method for triple gate nMOS devices with variation of channel length (90 a 910 nm) and temperature (200K to 77K).

Este trabalho tem como objetivo estudar o ponto invariante com a temperatura (ZTC - Zero Temperature Coefficient) para transistores com estrutura SOI UTBB (Silicon-On-Insulator Ultra-Thin Body and BOX) nMOSFETs em relação à influência do plano de terra (GP-Ground Plane) e da espessura do filme de silício (tSi). Este estudo foi realizado nas regiões linear e de saturação, por meio da utilização de dados experimentais e de um modelo analítico. Parâmetros elétricos, como a tensão de limiar e a transcondutância foram analisados para verificar a influência do plano de terra e da espessura de filme de silício (tSi), e para estudar a polarização, entre porta e fonte, que não varia com a temperatura (VZTC). Foram utilizados dispositivos com (concentração de 1018 cm-3) e sem (concentração de 1015 cm-3) plano de terra em duas lâminas diferentes, uma com 6 nm de tSi e outra com 14 nm de tSi. Foi observado, que a presença do GP aumenta o valor de VZTC, devido ao fato do GP eliminar os efeitos de substrato no dispositivo aumentando a tensão de limiar do mesmo, e este, é diretamente proporcional a VZTC. O VZTC mostrou ser inversamente proporcional com a diminuição do tSi. Todos os resultados experimentais de VZTC foram comparados com o modelo. Foi observada uma boa concordância entre os VZTC de 25 ºC a 150 ºC, sendo que o desvio padrão foi menor que 81 mV em todos os casos estudados. Para se observar o efeito de substrato na tensão de limiar foi utilizado um modelo analítico que leva em consideração o efeito da queda de potencial no substrato, o efeito de confinamento quântico e parâmetros do dispositivo a ser modelado. O VZTC mostrou ser maior na região de saturação devido ao aumento da transcondutância e da polarização entre dreno e fonte (VDS), em ambos dispositivos (com e sem GP), chegando a ter um aumento de 360 mV em alguns casos. / This work aims to study the zero temperature coefficient point (ZTC) for transistors with SOI UTBB nMOSFETs (Silicon-On-Insulator Ultra-Thin Body and BOX) structure regarding the influence of the ground plane (GP) and the thickness of the silicon film (tSi). This study was realized in the linear and saturation region, by the use of experimental data and an analytical model. Electrical parameters such as threshold voltage and transconductance were analyzed with the objective of verifying the influence of the ground plane and silicon film thickness (tSi) in the same, and to analyze the polarization, between gate and source, that have zero influence of the temperature (VZTC). Were used devices with (concentration 1018 cm-3) and without (concentration 1015 cm-3) ground plane on two different wafers, with 6 nm tSi and the other with 14 nm tSi. It was observed that the presence GP increases the value of VZTC, because GP eliminates substrate effects and as consequence, the threshold voltage of the device increase and this is directly proportional to VZTC. The VZTC showed to be inversional proportional to the reduction of tSi. All experimental results were compared with a simple model for VZTC and were observed a good convergence between the results, for VZTC from 25 ºC to 150 ºC, and the biggest standard error observed in all the devices was 81 mV. To observe the effect of substrate on the threshold voltage, was used an analytical model that takes into account the effect of potential drop on the substrate, the effect of quantum confinement and the device parameters to be modeled. The VZTC show to be higher in the saturation region, due the increase of transconductance and the polarization between drain and source (VDS), in both devices (with and without GP), reaching an increase of 360 mV in some cases.

Esse trabalho tem como objetivo estudar o comportamento de transistores de camada de silício e óxido enterrado ultrafinos (UTBB SOI nMOSFET) e transistores de nanofios horizontais com porta ômega ? (?G NW SOI MOSFET) com ênfase na variação da tensão aplicada no substrato (VGB). As análises foram feitas através de medidas experimentais e simulações numéricas. Nos dispositivos UTBB SOI nMOSFET foram estudados dispositivos com e sem implantação de plano de terra (GP), de três diferentes tecnologias, e com diferentes comprimentos de canal. A partir do modelo analítico de tensão de limiar desenvolvido por Martino et al. foram definidos os valores de VGB. A tecnologia referência possui 6 nm de camada de silício (tSi) e no óxido de porta uma camada de 5 nm de SiO2. A segunda tecnologia tem um tSi maior (14 nm) em relação a referência e a terceira tecnologia tem no óxido de porta um material de alta constante dielétrica, HfSiO. Na tecnologia de referência, os dispositivos com GP mostraram melhores resultados para transcondutância na região de saturação (gmSAT) devido ao forte acoplamento eletrostático entre a região da porta e do substrato. Porém os dispositivos com GP apresentam uma maior influência do campo elétrico longitudinal do dreno no canal, assim os parâmetros condutância de saída (gD) e tensão Early (VEA) são degradados, consequentemente o ganho de tensão intrínseco (AV) também. Na tecnologia com tSi de 14 nm, a influência do acoplamento eletrostático entre porta e substrato é menor em relação a referência, devido à maior espessura de tSi. Como a penetração do campo elétrico do dreno é maior em dispositivos com GP, todos os parâmetros analógicos estudados são degradados em dispositivos com GP. A última tecnologia estudada, não apresenta grande variação nos resultados quando comparadodispositivos com e sem GP. O AV, por exemplo, tem uma variação entre 1% e 3% comparando os dispositivos com e sem GP. Foram feitas análises em dispositivos das três tecnologias com comprimento de canal de 70 nm, e todos os parâmetros degradaram com a diminuição do comprimento de canal, como esperado. O fato de ter um comprimento de canal menor faz com que a influência do campo elétrico longitudinal do dreno seja mais relevante, degradando assim todos os parâmetros analógicos nos dispositivos com GP. Nos dispositivos ?G NW SOI MOSFET foram feitas análises em dispositivos pMOS e nMOS com diferentes larguras de canal (WNW = 220 nm, 40 nm e 10 nm) para diferentes VGB. Através de simulações viu-se que dispositivos com largura de canal de 40 nm possuem uma condução de corrente pela segunda interface para polarizações muito altas (VGB = +20 V para nMOS e VGB -20 V para pMOS). Todavia essa condução de corrente na segunda interface ocorre ao mesmo tempo que na primeira interface, impossibilitando fazer a separação dos efeitos de cada interface.A medida que a polarização no substrato faz com que haja uma condução na segunda interface, todos os parâmetros degradam devido a essa condução parasitária. Dispositivos estreitos sofrem menor influência de VGB e, portanto, tem os parâmetros menos degradados, diferente dos dispositivos largos que tem uma grande influência de VGB no comportamento elétrico do transistor. Quando a polarização no substrato é feita a fim de que não haja condução na segunda interface, a variação da inclinação de sublimiar entre dispositivos com WNW = 220 nm e 10 nm é menor que 2 mV/déc. Porém a corrente de dreno de estado ligado do transistor (ION) apresenta melhores resultados em dispositivos largos chegando a 6 vezes maior para nMOS e 4 vezes maior para pMOS que em dispositivos estreitos. Os parâmetros analógicos sofrem pouca influência da variação de VGB. Os dispositivos estreitos (WNW = 10 nm) praticamente têm resultados constantes para gmSAT, VEA e AV. Já os dispositivos largos (WNW = 220 nm) possuem uma pequena degradação de gmSAT para os nMOS, o que degrada levemente o AV em cerca de 10 dB. A eficiência do transistor (gm/ID) apresentou grande variação com a variação de VGB, piorando-a a medida que a segunda interface ia do estado de não condução para o estado de condução. Porém analisando os dados para a tensão que não há condução na segunda interface observou-se que, em inversão forte, a eficiência do transistor apresentou uma variação de 1,1 V-1 entre dispositivos largos (WNW = 220 nm) e estreitos (WNW = 10 nm). Com o aumento do comprimento do canal, esse valor de variação tende a diminuir e dispositivos largos passam a ser uma alternativa válida para aplicação nessa região de operação. / This work aims to study the behavior of the ultrathin body and buried oxide SOI nMOSFET (UTBB SOI nMOSFET) and the horizontal ?-gate nanowire SOI MOSFET (?G NW SOI MOSFET) with the variation of the back gate bias (VGB). The analysis were made through experimental measures and numerical simulation. In the UTBB SOI nMOSFET devices, devices with and without ground plane (GP) implantation of three different technologies were studied. Based on analytical model developed by Martino et al. the values VGB were defined. The reference technology has silicon film thickness (tSi) of 6 nm and 5 nm of SiO2 in the front oxide. The second technology has a thicker tSi of 14 nm comparing to the reference and the third technology has a high-? material in the front oxide, HfSiO. In the reference technology, the devices with GP shows better result for transconductance on saturation region (gmSAT) due to the strong coupling between front gate and substrate. However, devices with GP have major influence of the drain electrical field penetration, then the output conductance (gD) and Early voltage (VEA) are degraded, consequently the intrinsic voltage gain (AV) as well. In the technology with tSi of 14 nm, the influence of the coupling between front gate and substrate is lower because of the thicker tSi. Once the drain electrical field penetration is higher in devices with GP, all analog parameters are degraded in devices with GP. The third technology, presents results very close between devices with and without GP. The AV has a variation from 1% to 3% comparing devices with and withoutGP. Devices with channel length of 70 nm were analyzed and all parameters degraded with the decrease of the channel length, as expected. Due to the shorter channel length, the influence of the drain electrical field penetration is more relevant, degrading all the analog parameters in devices with GP. In the ?G NW SOI MOSFET devices, the analysis were done in nMOS and pMOS devices with different channel width (WNW = 220 nm, 40 nm and 10 nm) for different VGB. By the simulations, devices with channel width of 40 nm have a conduction though the back interface for very high biases (+20 V for nMOS and -20 V for pMOS). However, this conduction occurs at the same time as in the front interface, so it is not possible to separate de effects of each interface. As the substrate bias voltage induces a back gate current, all the parameters are degraded due to this parasitic current. Narrow devices are less affected by VGB and thus its parameters are less degraded, different from wider devices, in which VGB has a greater influence on their behavior. When the back gate is biased in order to avoid the conduction in back interface, the subthreshold swing variation between devices with WNW = 220 nm and 10 nm is lower than 2 mV/déc. However, the on state current (ION) has better results in wide devices reaching 6 times bigger for nMOS and 4 times bigger for pMOS The analog parameterssuffer little influence of the back gate bias variation. The narrow devices (WNW = 10 nm) have practically constant results gmSAT, VEA and AV. On the other hand, wide devices (WNW = 220 nm) have a small degradation in the gmSAT for nMOS, which slightly degrades de AV. The transistor efficiency showed great variation with the back gate bias variation, worsening as the back interface went from non-conduction state to conduction state. However, when the back gate is biased avoiding the conduction in back interface, the transistor efficiency for strong inversion region has a small variation of 1,1 V-1 between wide (WNW = 220 nm) and narrow (WNW = 10 nm) devices. As the channel length increases, this value of variation tends to decrease and wide devices become a valid alternative for applications in this region of operation.

Longtemps considérées comme néfastes, les contraintes sont devenues un des moyens principaux pour améliorer les performances des dispositifs métal-oxyde-semiconducteur (MOS). En effet, les déformations générées augmentent sensiblement la mobilité des porteurs dans le silicium. C'est dans ce cadre que j'ai étudié, par holographie électronique en champ sombre (DFEH), les déformations cristallines engendrées par certaines étapes clés du procédé de fabrication de transistors planaires de dernière génération, totalement déplétés car réalisés sur des substrats silicium sur isolant (FD-SOI). La DFEH est une technique de microscopie électronique en transmission (TEM), récemment inventée au CEMES, qui permet de cartographier les déformations cristallines avec une résolution spatiale nanométrique et une précision de 10-4 sur des champs de vue micrométriques. J'ai mis au point et utilisé des modélisations par éléments finis afin de comprendre puis reproduire mes résultats expérimentaux et ainsi identifier les phénomènes mécaniques mis en jeu au cours de différentes étapes. Après avoir prouvé que la DFEH est adaptée à la mesure des champs de déformation dans les structures MOS FDSOI (couche superficielle de Si désorientée vis-à-vis du substrat de référence), je me suis intéressé au procédé de conversion de films minces de Si en SiGe, par la méthode dite de "condensation de germanium". J'ai montré que cette technique permet d'obtenir des films minces de type SiGe (SGOI) pseudomorphes, de composition variable. Les déformations hors plan mesurées par DFEH mettent en évidence les deux mécanismes affectant la redistribution du Ge (diffusion et injection), dont l'importance relative dépend de la température à laquelle s'effectue le procédé. De plus, j'ai montré que ces films minces SGOI, initialement contraints, se relaxaient très fortement lors de leur gravure en vue de la fabrication de substrats co-intégrés SOI/SGOI. J'ai pu identifier que cet effet, initialement observé à partir de mesures électriques et connu sous le nom d'effet "SA/SB", ne pouvait être dû qu'à des caractéristiques mécaniques dégradées de l'interface SiGe/SiO2. Je me suis ensuite intéressé à certaines des étapes clés de la fabrication du transistor suspectées de modifier l'état de déformation de la structure, telles que la fabrication de l'empilement de grille et des sources/drains ainsi que de la siliciuration nécessaire à la prise des contacts. J'ai pu expliquer en quoi et pourquoi ces étapes impactaient l'état final de déformation du canal du transistor et donc ses performances. Par ailleurs, je montre comment et dans quelles limites la DFEH peut être utilisée pour mesurer des concentrations de dopants, en conservant une résolution nanométrique. J'ai particulièrement étudié le cas (favorable) du bore dans le silicium et, après couplage à des mesures électriques, j'ai ainsi pu calculer le coefficient reliant les déformations mesurées aux concentrations de bore en substitution. Finalement, j'ai comparé et discuté des différences entre informations fournies par DFEH et par diffraction de rayons X haute résolution. Une annexe complète ce travail et discute des conditions optiques et d'utilisation optimales des sources à émission de champ Schottky équipant un TEM, notamment de la contribution des lobes d'émission latérale sur le degré de cohérence de la sonde. / After being considered harmful for a long time, stress became one of the principal means to improve metal-oxide-semiconductor (MOS) device performance. Indeed, the generated strains significantly increase carrier mobility in silicon. Within this context, I used dark-field electron holography (DFEH) to study the crystalline strains generated by some key steps of the manufacturing process of latest generation of planar transistors, fully depleted as produced on silicon on insulator substrates (FD-SOI). DFEH is a transmission electron microscopy (TEM) technique, recently invented at CEMES, which allows crystalline strain to be mapped with nanometric resolution and an accuracy of 10-4 over micrometric fields of view. I developed and used finite element models in order to understand, then reproduce, my experimental results and thus identify the mechanical phenomena involved during different processing steps. After proving that DFEH is suitable for strain fields mapping in FDSOI MOS structures (Si surface layer disorientated in respect of the reference substrate), I have been interested in the conversion process of thin Si films into SiGe, by a method known as "germanium condensation". I showed that this technique enables pseudomorphous thin SiGe films (SGOI) of variable composition to be obtained. The out-of-plane strain measured by DFEH emphasises the two mechanisms affecting the Ge redistribution (diffusion and injection), whose relative importance depends on the temperature of the process. Moreover, I showed that these thin SGOI films, initially stressed, relax strongly during the etching carried out to manufacture co-integrated SOI/SGOI substrates. I could identify that this effect, initially observed by electrical measurements and known as "SA/SB" effect, can only be explained by a degradation of the mechanical characteristics of the SiGe/SiO2 interface. I have also been interested in some of the key steps of the transistor manufacturing suspected to modify the structural strain state, such as the grid stack and sources/drains processes, as well as salicidation necessary to form the contacts. I was able to explain how and why these steps impact the final strain state of the transistor channel and thus its performance. In a separate development, I have shown how DFEH can be used to measure doping concentrations while preserving a nanometric resolution, and discuss its limits. I studied in particular the (favourable) case of boron doping in silicon and, after electrical measurements coupling, I calculated the coefficient connecting the measured strains to the boron substitution concentrations. Finally, I compared and discussed the differences between information obtained by DFEH and high resolution X-ray diffraction. An appendix completes this work and discusses the optical and optimal use conditions of Schottky field emission sources equipping a TEM, in particular the contribution of side-emission lobes on the degree of coherence of the probe.

Avec la diminution constante des dimensions des dispositifs électroniques, les structures MOS font face à de nombreux effets physiques liés à la miniaturisation. Dans le but de maintenir le rythme d'intégration indiqué par la loi de Moore, des nouvelles technologies, dont la structure résiste plus à ces effets physiques, remplacerons le transistor MOSFET bulk. Les modèles physiques permettant de prédire le comportement des transistors MOS atteignent rapidement leurs limites quand ils sont appliqués à ces structures émergentes. Ce travail de thèse est consacré au développement des modèles numériques et analytiques dédiés à la caractérisation des nouvelles architectures SOI et à substrat massif. Nous nous focalisons sur la modélisation du courant de drain basée sur le potentiel de surface, ainsi qu'à la modélisation du comportement en bruit basse fréquence de ces nouveaux dispositifs. Nous proposons un modèle explicite décrivant les potentiels de surface avant et arrière d'une structure SOI. Nous développons ensuite un modèle de bruit numérique et analytique permettant de caractériser les différents oxydes d'une structure FD SOI. La dernière partie de ce mémoire est consacrée à l'étude d'une nouvelle architecture du transistor MOS sur substrat massif. Une caractérisation de la conduction électrique de ce dispositif et de son comportement en bruit basse fréquence sont présentés / With the continuous reduction of the size of MOS devices, various associated short channel effects become significant and limit this scaling. To restrain this limit, multi-gate MOSFET devices seem to be more interesting, thanks to their better control of the gate on the channel. These new devices seem to be good candidates to replace the classical MOS architecture. The existing physical models used to predict the behaviour of MOSFET bulk devices are limited when they are applied to these emerging structures. This thesis is devoted to the development of numerical and analytical models dedicated to the characterization of new SOI architectures and bulk devices. We focus on the modeling of the drain current based on the surface potential as well was the modeling of the low frequency noise behaviour of these devices. We propose an explicit model describing the front and back surface potential of a FD SOI structure. We then develop numerical and analytical low frequency noise models allowing the characterization of the different oxides of a FD SOI structure. The last part of this thesis is devoted to the study of a new architecture of bulk MOS transistors. A characterization of the electrical conduction of this device and its low frequency noise behavior are presented

Cette thèse est consacrée à la caractérisation et la modélisation du transport électronique dans des matériaux et dispositifs SOI avancés pour la microélectronique. Tous les matériaux innovants étudiés(ex: SOI fortement dopé, plaques obtenues par collage etc.) et les dispositifs SOI sont des solutions possibles aux défis technologiques liés à la réduction de taille et à l'intégration. Dans ce contexte,l'extraction des paramètres électriques clés, comme la mobilité, la tension de seuil et les courants de fuite est importante. Tout d'abord, la caractérisation classique pseudo-MOSFET a été étendue aux plaques SOI fortement dopées et un modèle adapté pour l'extraction de paramètres a été proposé. Nous avons également développé une méthode électrique pour estimer la qualité de l'interface de collage pour des plaquettes métalliques. Nous avons montré l'effet bipolaire parasite dans des MOSFET SOI totalement désertés. Il est induit par l’effet tunnel bande-à-bande et peut être entièrement supprimé par une polarisation arrière. Sur cette base, une nouvelle méthode a été développée pour extraire le gain bipolaire. Enfin, nous avons étudié l'effet de couplage dans le FinFET SOI double grille, en mode d’inversion. Un modèle analytique a été proposé et a été ensuite adapté aux FinFETs sans jonction(junctionless). Nous avons mis au point un modèle compact pour le profil des porteurs et des techniques d’extraction de paramètres. / This thesis is dedicated to the electrical characterization and transport modeling in advanced SOImaterials and devices for ultimate micro-nano-electronics. SOI technology is an efficient solution tothe technical challenges facing further downscaling and integration. Our goal was to developappropriate characterization methods and determine the key parameters. Firstly, the conventionalpseudo-MOSFET characterization was extended to heavily-doped SOI wafers and an adapted modelfor parameters extraction was proposed. We developed a nondestructive electrical method to estimatethe quality of bonding interface in metal-bonded wafers for 3D integration. In ultra-thin fully-depletedSOI MOSFETs, we evidenced the parasitic bipolar effect induced by band-to-band tunneling, andproposed new methods to extract the bipolar gain. We investigated multiple-gate transistors byfocusing on the coupling effect in inversion-mode vertical double-gate SOI FinFETs. An analyticalmodel was proposed and subsequently adapted to the full depletion region of junctionless SOI FinFETs.We also proposed a compact model of carrier profile and adequate parameter extraction techniques forjunctionless nanowires.

Cette étude de philosophie comparée propose une herméneutique de l’idée de soi à partir d’une analyse de la dimension ascétique de la question « quel soi ? », qui se manifeste à travers les disciplines de libération mises en place par les traditions du Portique et du Zen. Déclinée sous différentes formes, cette question constitue la pierre angulaire des pratiques de soi propres aux deux traditions. Il apparaît que sa principale fonction est celle d’orienter l’idée de soi, eu égard à une polarité soi ↔ non-soi, afin de parvenir à la condition du sage, celle d’un accord libérateur avec une nature originelle commune à tous. Ainsi, au lieu de désigner simplement un fondement ontologique – réel ou supposé – l’idée de soi joue alors bien plutôt un rôle de vecteur, qui, selon son orientation,permet ou non d’actualiser cet accord. Par la prise en compte comparative du rôle de la négation (détachement) de soi, cette étude cherche donc à élargir le spectre des processus de subjectivation ou des pratiques de soi et, ainsi, de mettre au jour un aspect assez négligé par l’histoire occidentale de la subjectivité. Par là même, cette thèse permet de mieux comprendre comment une (méta)physique stoïcienne du plein peut être à même de penser la négation (détachement) de soi et, inversement, comment une métaphysique bouddhiste de la vacuité peut développer une pensée de la subjectivité morale et de la responsabilité / This study in comparative philosophy offers a hermeneutics of the idea of self. It explores the ascetic dimension of the question “what self?” apparent across the various disciplines of liberation developed by the Stoic and Zen traditions. In its diverse guises, this question is the cornerstone of specific practices of the self within these traditions. As such, its main function is to guide the idea of self, with regard to the polarity self ↔ non-self, in order to achieve the status of the sage, which represents a kind of harmony with an original nature that is common to all individuals. Therefore, rather than simply designating an ontological foundation – real or alleged – the idea of self has the role of a vector, which, depending on its orientation, allows one to actualise (or not) this harmony. Through comparative analysis of the role of negation (detachment) of the self, this study seeks to broaden the spectrum of the processes of subjectification or practices of the self and, thus, to bring to light an aspect that has been somewhat neglected by the Western history of subjectivity. In doing so, this thesis enables better understanding of how the full-bodied (meta)physics of the Stoics is able to think the negation (detachment) of the self and, conversely, of how the Buddhist metaphysics of emptiness can develop an idea of moral subjectivity and responsibility