Indiana University-Purdue University Indianapolis (IUPUI) / This thesis presents a converter topology for photovoltaic panels. This topology minimizes the number of switching devices used, thereby reducing power losses that arise from high frequency switching operations. The control strategy is implemented using a simple micro-controller that implements the proportional plus integral control. All the control loops are closed feedback loops hence minimizing error instantaneously and adjusting efficiently to system variations. The energy management between three components, namely, the photovoltaic panel, a battery and a DC link for a microgrid, is shown distributed over three modes. These modes are dependent on the irradiance from the sunlight. All three modes are simulated. The maximum power point tracking of the system plays a crucial role in this configuration, as it is one of the main challenges tackled by the control system. Various methods of MPPT are discussed, and the Perturb and Observe method is employed and is described in detail. Experimental results are shown for the maximum power point tracking of this system with a scaled down version of the panel's actual capability.

台灣歷經過去幾十來在電子工業的蓬勃發展，帶動了供應鏈上各種產業聚落的形成。舉凡終端產品如個人電腦、筆記型電腦、無線通信及影音設備等。關鍵電子零組件如電源供應器、印刷電路板、積體電路代工業等。電源供應器(Power Supply) 提供各種電子產品穩定的電壓電源，隨著各式電子產品的演進，電源供應器產業的公司也不斷的進行各種創新研發與經營策略的調整。 本研究以T公司為個案研究對象，探討台灣電源供應器產業在以往的成長經驗裡，在經營策略面與創新模式中，有哪些關鍵成功因素。經由外在環境探討與內部組織優劣勢分析(SWOT)，以及公司現行策略類型之整理（司徒達賢2005），本研究進行個案公司可行性策略之研擬、分析與建議(TOWS)。個案公司於實體及虛擬通路市場有多年的經營與成功經驗，舉凡創新研發與專利佈局、多品牌全球交叉行銷、以核心領域擴散之產品多角化經營路線等。本個案是一個台灣中小企業在極大化有利的外在機會與創新研發的強項下，成功的達成逐步成長的目標並進而完成台灣OTC市場上櫃的案例。 由於2008年以來的金融風暴及今年歐美市場在主權債務問題與全球經濟疲弱的表現，僅少數廠商仍有逆勢成長的表現；對於未來電源供應器產業的景氣看法，也看法分歧。本研究透過系統性的分析工具，從總體經濟面與產業面的威脅與機會及內部組織的優劣勢分析出發，推衍出對未來經營策略的具體方針與策略執行方案。可做為個案公司對未來發展經營策略之建議以及科技相關產業或其他企業在經營策略分析、行銷通路佈局之參考。 本研究探討之主要經營創新策略關鍵重要因素，包含了多品牌全球互動行銷、逆循環行銷模式、搭配專利進行顛覆式研發創新、少量多樣模組化生產等創新經營模式。以上因素也造就了個案公司過去連續多年成長倍增的驅動力量。 關鍵字：電源供應器、多品牌全球交叉行銷、TOWS

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.

Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predictable timing signals, called clocks, which must be distributed to a large number of sequential elements. Collectively, these clocks have a significant impact on the frequency of operation and, consequently, on the performance of the systems. The clocks are also responsible for a large fraction of the power consumed by these systems. The objective of this dissertation is to better understand clock distribution in order to identify opportunities and strategies for improvement by analyzing the conditions under which the optimal tradeoff between power and performance can be achieved, by modeling the constraints associated with local and global clocking, by evaluating the impact of noise, and by investigating promising new design strategies for future integrated systems.

The use of SMPS (Switched mode power supply) in embedded systems is continuously increasing. The technological requirements of these systems include simultaneously a very good voltage regulation and a strong compactness of components. SEPIC ( Single-Ended Primary Inductor Converter) is a DC/DC switching converter which possesses several advantages with regard to the other classical converters. Due to the difficulty in control of its 4th-order and non linear property, it is still not well-exploited. The objective of this work is the development of successful strategies of control for a SEPIC converter on one hand and on the other hand the effective implementation of the control algorithm developed for embedded applications (FPGA, ASIC) where the constraints of Silicon surface and the loss reduction factor are important. To do it, two non linear controls and two observers of states and load have been studied: a control and an observer based on the principle of sliding mode, a deadbeat predictive control and an Extended Kalman observer. The implementation of both control laws and the Extended Kalman observer are implemented in FPGA. An 11-bit digital PWM has been developed by combining a 4-bit Δ-Σ modulation, a 4-bit segmented DCM (Digital Clock Management) phase-shift and a 3-bit counter-comparator. All the proposed approaches are experimentally validated and constitute a good base for the integration of embedded switching mode converters

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.

Les réseaux de capteurs sans fil nécessitent des fonctions de calcul et de transmissionradio associées à chaque capteur. Les SoCs RF intégrant ces fonctions doivent avoir uneautonomie la plus grande possible et donc une très faible consommation. Aujourd'hui, leursperformances énergétiques pourraient être fortement améliorées par des systèmes d'alimentationinnovants. En effet, les circuits d'alimentation remplissent leur fonction classique de conversiond'énergie mais aussi des fonctions d'isolation des blocs RF et digitaux. Leurs performancess'évaluent donc en termes d'efficacité énergétique et de réponse transitoire mais aussi d'isolationentre blocs et de réjection de bruit.Ce travail de thèse concerne l'intégration du système de gestion et de distribution del’énergie aux différents blocs RF d’un émetteur/récepteur en élaborant une méthodologie « topdown» pour déterminer la sensibilité de chaque bloc à son alimentation et en construisant unearchitecture innovante et dynamique de gestion/distribution de l'énergie sur le SoC. Cetteméthodologie repose sur la disponibilité de régulateurs de tension présentant des performancesadaptées. Un deuxième volet du travail de thèse a donc été de réaliser un régulateur linéaire detype LDO à forte réjection sur une bande passante relativement large et bien adapté àl'alimentation de blocs RF très sensibles aux bruits de l'alimentation. / Wireless sensor networks require calculation functions and radiofrequencytransmission modules within each sensor. RF SoCs integrating these functions must have thebiggest battery life and so a very small consumption. Today, innovative power managementsystems could highly enhance the energy performances of this type of RF SoC. Indeed, thesepower systems perform energy conversion and also the isolation functions of RF and digitalblocks. Their features are thus estimated in terms of energy efficiency, transient response and alsoisolation between blocks and noise rejection.This thesis work concerns the integration of the power management systems and itsdistribution channels into different ultra-low-power SoCs. This was achieved mainly thanks to thedevelopment of a new “top-down” approach. This new methodology consists of determining thesensibility of every block to its power supply and of designing an innovative and dynamicarchitecture of power management circuits on the SoC. This study ends up in the implementationof a very efficient low dropout (LDO) regulator for noise-sensitive low-current RF blocks inmixed SoC applications. The fabricated prototype achieves a high power supply rejection for awide range of frequencies.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This Master Thesis presents the development of a new dynamic model for the DC-DC Zero-Voltage-Switching Phase-Shift-Modulated Full-Bridge (ZVS-PSM-FB).At first, the ZVSPSM-FB converter is analyzed and the Steady-State equations are derived. Then, using the ac equivalent circuit modeling technique, it is derived two new ZVS-PSM-FB dynamical models, based on step operation of the converter and steady-state converter equations. These two new ZVS-PSM-FB dynamical models with two dynamical models previously presented in the literature are used to perform a frequency response and a transfer-function DC-gain comparison to verify the performance of the dynamical models. Comparison results shows that our second model here derived presents a better performance among other models, keeping the desirable characteristics as simple polynomial ratio transfer-functions, excellent theoretical accuracy of transfer-functions DC-gains, transfer-functions coefficients independency of circuit parasitics components, excepting the primary leakage inductance. Even in this work, it is shown frequency response experimental results of the ZVS-PSM-FB converter, designed following telecommunications rectifiers power supplies standards. / Esta Dissertação de Mestrado apresenta o desenvolvimento de um novo modelo dinâmico para o conversor CC-CC Ponte-Completa Modulado por Deslocamento de Fase e com Comutação em Zero de Tensão (ZVS-PSM-FB). Inicialmente, o conversor ZVS-PSM-FB é analisado, onde são derivadas as equações que definem a operação em regime-permanente do conversor. A seguir, utilizando-se da técnica de modelagem ca média de conversores estáticos, deriva-se dois novos modelos dinâmicos para o conversor, tendo por base as etapas de operação do conversor e as equações de regime-permanente. Feito isso, os dois modelos aqui derivados, são comparados com outros dois modelos dinâmicos já apresentados na literatura para verificar seus desempenhos quanto à resposta em freqüência e resposta do ganho-cc das funções de transferências à variações de carga do conversor, dos modelos dinâmicos. Resultados desta comparação mostram que o segundo modelo aqui derivado é o que apresenta melhor desempenho entre os modelos comparados, mantendo características desejáveis de simples formato de função de transferência como razão de polinômios, precisão teórica excelente para resposta de ganho-cc das funções de transferências e não-dependência dos coeficientes das funções de transferências de parâmetros parasitas do circuito, a menos da indutância de dispersão do transformador. Ainda neste trabalho, são mostrados resultados experimentais da resposta em freqüência do conversor ZVS-PSM-FB, projetado com especificações de normas para retificadores chaveados de alta-freqüência para equipamentos de telecomunicações.

L’émergence des circuits complexes numériques, ou System-On-Chip (SOC), pose notamment la problématique de la consommation énergétique. Parmi les blocs fonctionnels significatifs à ce titre, apparaissent les mémoires et en particulier les mémoires statiques (SRAM). La maîtrise de la consommation énergétique d’une mémoire SRAM inclue la capacité à rendre la mémoire fonctionnelle sous très faible tension d’alimentation, avec un objectif agressif de 300 mV (inférieur à la tension de seuil des transistors standard CMOS). Dans ce contexte, les travaux de thèse ont concerné la proposition d’un point mémoire SRAM suffisamment performant sous très faible tension d’alimentation et pour les nœuds technologiques avancés (CMOS bulk 28nm et FDSOI 28nm). Une analyse comparative des architectures proposées dans l’état de l’art a permis d’élaborer deux points mémoire à 10 transistors avec de très faibles impacts de courant de fuite. Outre une segmentation des ports de lecture, les propositions reposent sur l’utilisation de périphéries adaptées synchrones avec notamment une solution nouvelle de réplication, un amplificateur de lecture de données en mode tension et l’utilisation d’une polarisation dynamique arrière du caisson SOI (Body Bias). Des validations expérimentales s’appuient sur des circuits en technologies avancées. Enfin, une mémoire complète de 32kb (1024x32) a été soumise à fabrication en 28 FDSOI. Ce circuit embarque une solution de test (BIST) capable de fonctionner sous 300mV d’alimentation. Après une introduction générale, le 2ème chapitre du manuscrit décrit l’état de l’art. Le chapitre 3 présente les nouveaux points mémoire. Le 4ème chapitre décrit l’amplificateur de lecture avec la solution de réplication. Le chapitre 5 présente l’architecture d’une mémoire ultra basse tension ainsi que le circuit de test embarqué. Les travaux ont donné lieu au dépôt de 4 propositions de brevet, deux conférences internationales, un article de journal international est accepté et un autre vient d’être soumis. / Emergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal.

The thesis shows the historical development of the South Moravian electricity system and the development of Brno´s network is discussed in more detail, especially the current form of the network from the outskirts of the city to its historical centre. The lattice network, as a subject of the analysis, is described in terms of the operation and reliability of the power supply. It also informs about the gradual development of the technology applied in the lattice network Brno-střed. The practical part performs the analysis of theoretical data and recorded data with respect to steady-state and faulty-state operation of the lattice network Brno-střed. The theoretical analysis is based on the simulation and calculation of the lattice network model in the software PAS DAISY Bizon and the monitored parameter is the transformers power load. In addition, the analysis of the real data includes the assessment of the difference average phase current values, as well as voltage, between the transformer phases. There is also the evaluation of the energy flow from the low voltage side to the high voltage side of the analysed network.