Modern cities are undergoing rapid expansion. The number of connected devices in the networks in and around these cities is increasing every day and will exponentially increase in the next few years. At home, the number of connected devices is also increasing with the introduction of home automation appliances and applications. Many of these appliances are becoming smart devices which can track our daily routines. It is imperative that all these devices should be secure. When cryptographic keys used for encryption and decryption are stored on memory present on these devices, they can be retrieved by attackers or adversaries to gain control of the system. For this purpose, Physical Unclonable Functions (PUFs) were proposed to generate the keys required for encryption and decryption of the data or the communication channel, as required by the application. PUF modules take advantage of the manufacturing variations that are introduced in the Integrated Circuits (ICs) during the fabrication process. These are used to generate the cryptographic keys which reduces the use of a separate memory module to store the encryption and decryption keys. A PUF module can also be recon gurable such that the number of input output pairs or Challenge Response Pairs (CRPs) generated can be increased exponentially. This dissertation proposes three designs of PUFs, two of which are recon gurable to increase the robustness of the system.

No description available.

Amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) constitute the central theme of this thesis. Within this theme, three primary areas of focus are pursued. The first focus is the realization of a transparent three-stage ring oscillator with buffered output and an output frequency in the megahertz range. This leads to the possibility of transparent radio frequency applications, such as transparent RFID tags. At the time of its fabrication, this ring oscillator was the fastest oxide electronics ring oscillator reported, with an output frequency of 2.16 MHz, and a time delay per stage of 77 ns. The second focus is to ascertain whether a three-terminal device (i.e., a TFT) is an appropriate structure for conducting space-charge-limited-current (SCLC) measurements. It is found that it is not appropriate to use a diode-tied or gate-biased TFT configuration for conducting a SCLC assessment since square-law theory shows that transistor action alone gives rise to I proportional to V² characteristics, which can easily be mistakenly attributed to a SCLC mechanism. Instead, a floating gate TFT configuration is recommended for accomplishing SCLC assessment of AOS channel layers. The final focus of this work is to describe an assessment procedure appropriate for determining if a dielectric is suitable for use as a TFT gate insulator. This is accomplished by examining the shape of a MIM capacitor's log(J)-ξ curve, where J is the measured current density and ξ is the applied electric field. An appropriate dielectric for use as a TFT gate insulator will have a log(J)-ξ curve that expresses a clear breakover knee, indicating a high-field conduction mechanism dominated by Fowler-Nordheim tunneling. Such a dielectric produces a TFT with a minimal gate leakage which does not track with the drain current in a log(I[subscript D])-V[subscript GS] transfer curve. An inappropriate dielectric for use as a TFT gate insulator will have a log(J)-ξ curve that does not express a clear breakover knee, indicating that the dominate conduction mechanism is defect driven (i.e., pin-hole like shunt paths) and, therefore, the dielectric is leaky. It is shown that experimental log(J)-ξ leakage curves can be accurately simulated using Ohmic, space-charge-limited current (SCLC), and Fowler-Nordheim tunneling conduction mechanisms. / Graduation date: 2010

L’avantage de cette architecture FDSOI par rapport à l’architecture Si-bulk est qu’elle possède une face arrière qui peut être utilisée comme une deuxième grille permettant de moduler la tension de seuil Vth du transistor. Pour améliorer les performances des transistors canal p (PMOS), du Germanium est introduit dans le canal (SiGe) et au niveau des sources/drain pour la technologie 14nm FDSOI. Par ailleurs, la réduction de la géométrie des transistors à ces dimensions nanométriques fait apparaître des effets de design physique qui impactent à la fois les performances et la fiabilité des transistors.Ce travail de recherche est développé sur quatre chapitres dont le sujet principal porte sur les performances et la fiabilité des dernières générations CMOS soumises aux mécanismes de dégradation BTI (Bias Temperature Instability) et par injections de porteurs chauds (HCI) dans les dernières technologies 28nm et 14nm FDSOI. Dans le chapitre I, nous nous intéressons à l’évolution de l’architecture du transistor qui a permis le passage des nœuds Low-Power 130-40nm sur substrat silicium à la technologie FDSOI (28nm et 14nm). Dans le chapitre II, les mécanismes de dégradation BTI et HCI des technologies 28nm et 14nm FDSOI sont étudiés et comparés avec les modèles standards utilisés. L’impact des effets de design physique (Layout) sur les paramètres électriques et la fiabilité du transistor sont traités dans le chapitre III en modélisant les contraintes induites par l’introduction du SiGe. Enfin le vieillissement et la dégradation des performances en fréquence ont été étudiés dans des circuits élémentaires de type oscillateurs en anneau (ROs), ce qui fait l’objet du chapitre IV. / The subject of this thesis developed on four chapters, aims the development of advanced CMOS technology nodes fabricated by STMicroelectronics in terms of speed performance and reliability. The main reliability issues as Bias Temperature Instability (BTI) and Hot-Carriers (HC) degradation mechanisms have been studied in the most recent 28nm and 14nm FDSOI technologies nodes. In the first chapter, we presents the evolution of transistor architecture from the low-power 130-40nm CMOS nodes on silicon substrate to the recent FDSOI technology for 28nm and 14nm CMOS nodes. The second chapter presents the specificity of BTI and HCI degradation mechanisms involved in 28nm and 14nm FDSOI technology nodes. In the third chapter, we have studied the impact of layout effects on device performance and reliability comparing symmetrical and asymmetrical geometries. Finally the trade-off between performance and reliability is studied in the fourth chapter using elementary circuits. The benefit of using double gate configuration with the use of back bias VB in FDSOI devices to digital cells, allows to compensate partially or totally the aging in ring oscillators (ROs) observed by the frequency reduction. This new compensation technique allows to extend device and circuit lifetime offering a new way to guaranty high frequency performance and long-term reliability.

First, a frequency synthesizer for IEEE 802.15.4 / ZigBee transceiver applications that employs dynamic True Single Phase Clocking (TSPC) circuits in its frequency dividers is presented and through the analysis and measurement results of this synthesizer, the need for low power circuit techniques in frequency dividers is discussed. Next, Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cells are explored for implementing radio-frequency (RF) frequency dividers of low power frequency synthesizers. DCVSL ip- ops offer small input and clock capacitance which makes the power consumption of these circuits and their driving stages, very low. We perform a delay analysis of DCVSL circuits and propose a closed-form delay model that predicts the speed of DCVSL circuits with 8 percent worst case accuracy. The proposed delay model also demonstrates that DCVSL circuits suffer from a large low-to-high propagation delay ( PLH) which limits their speed and results in asymmetrical output waveforms. Our proposed enhanced DCVSL, which we call DCVSL-R, solves this delay bottleneck, reducing PLH and achieving faster operation. We implement two ring-oscillator-based voltage controlled oscillators (VCOs) in 0.13 mu m technology with DCVSL and DCVSL-R delay cells. In measurements, for the same oscillation frequency (2.4GHz) and same phase noise (-113dBc/Hz at 10MHz), DCVSL-R VCO consumes 30 percent less power than the DCVSL VCO. We also use the proposed DCVSL-R circuit to implement the 2.4GHz dual-modulus prescaler of a low power frequency synthesizer in 0.18 mu m technology. In measurements, the synthesizer exhibits -135dBc/Hz phase noise at 10MHz offset and 58 mu m settling time with 8.3mW power consumption, only 1.07mWof which is consumed by the dual modulus prescaler and the buffer that drives it. When compared to other dual modulus prescalers with similar division ratios and operating frequencies in literature, DCVSL-R dual modulus prescaler demonstrates the lowest power consumption. An all digital phase locked loop (ADPLL) that operates for a wide range of frequencies to serve as a multi-protocol compatible PLL for microprocessor and serial link applications, is presented. The proposed ADPLL is truly digital and is implemented in a standard complementary metal-oxide-semiconductor (CMOS) technology without any analog/RF or non-scalable components. It addresses the challenges that come along with continuous wide range of operation such as stability and phase frequency detection for a large frequency error range. A proposed multi-bit bidirectional smart shifter serves as the digitally controlled oscillator (DCO) control and tunes the DCO frequency by turning on/off inverter units in a large row/column matrix that constitute the ring oscillator. The smart shifter block is completely digital, consisting of standard cell logic gates, and is capable of tracking the row/column unit availability of the DCO and shifting multiple bits per single update cycle. This enables fast frequency acquisition times without necessitating dual loop fi lter or gear shifting mechanisms. The proposed ADPLL loop architecture does not employ costly, cumbersome DACs or binary to thermometer converters and minimizes loop filter and DCO control complexity. The wide range ADPLL is implemented in 90nm digital CMOS technology and has a 9-bit TDC, the output of which is processed by a 10-bit digital loop filter and a 5-bit smart shifter. In measurements, the synthesizer achieves 2.5GHz-7.3GHz operation while consuming 10mW/GHz power, with an active area of 0.23 mm2.

<div> <div> <p>Phase transition materials (PTM) have garnered immense interest in concurrent post-CMOS electronics, due to their unique properties such as - electrically driven abrupt resistance switching, hysteresis, and high selectivity. The phase transitions can be attributed to diverse material-specific phenomena, including- correlated electrons, filamentary ion diffusion, and dimerization. In this research, we explore the application space for these materials through extensive device-circuit co-design and propose new ideas harnessing their unique electrical properties. The abrupt transitions and high selectivity of PTMs enable steep (< 60 mV/decade) switching characteristics in Hyper-FET, a promising post-CMOS transistor. We explore device-circuit co-design methodology for Hyper-FET and identify the criterion for material down-selection. We evaluate the achievable voltage swing, energy-delay trade-off, and noise response for this novel device. In addition to the application in low power logic device, PTMs can actively facilitate non-volatile memory design. We propose a PTM augmented Spin Transfer Torque (STT) MRAM that utilizes selective phase transitions to boost the sense margin and stability of stored data, simultaneously. We show that such selective transitions can also be used to improve other MRAM designs with separate read/write paths, avoiding the possibility of read-write conflicts. Further, we analyze the application of PTMs as selectors in cross-point memories. We establish a general simulation framework for cross-point memory array with PTM based <i>selector</i>. We explore the biasing constraints, develop detailed design methodology, and deduce figures of merit for PTM selectors. We also develop a computationally efficient compact model to estimate the leakage through the sneak paths in a cross-point array. Subsequently, we present a new sense amplifier design utilizing PTM, which offers built-in tunable reference with low power and area demand. Finally, we show that the hysteretic characteristics of unipolar PTMs can be utilized to achieve highly efficient rectification. We validate the idea by demonstrating significant design improvements in a <i>Cockcroft-Walton Multiplier, </i>implemented with TS based rectifiers. We emphasize the need to explore other PTMs with high endurance, thermal stability, and faster switching to enable many more innovative applications in the future.</p></div></div>

In der vorliegenden Arbeit werden rekurrente neuronale Netze im Hinblick auf ihre Eignung zur Bewegungssteuerung autonomer Roboter untersucht. Nacheinander werden Oszillatoren für Vierbeiner, homöostatische Ringmodule für segmentierte Roboter und monostabile Neuromodule für Roboter mit vielen Freiheitsgraden und komplexen Bewegungsabläufen besprochen. Neben dem mathematisch-theoretischen Hintergrund der Neuromodule steht in gleichberechtigter Weise deren praktische Implementierung auf realen Robotersystemen. Hierzu wird die funktionale Einbettung ins Gesamtsystem ebenso betrachtet, wie die konkreten Aspekte der zugrundeliegenden Hardware: Rechengenauigkeit, zeitliche Auflösung, Einfluss verwendeter Materialien und dergleichen mehr. Interessante elektronische Schaltungsprinzipien werden detailliert besprochen. Insgesamt enthält die vorliegende Arbeit alle notwendigen theoretischen und praktischen Informationen, um individuelle Robotersysteme mit einer angemessenen Bewegungssteuerung zu versehen. Ein weiteres Anliegen der Arbeit ist es, aus der Richtung der klassischen Ingenieurswissenschaften kommend, einen neuen Zugang zur Theorie rekurrenter neuronaler Netze zu schaffen. Gezielte Vergleiche der Neuromodule mit analogen elektronischen Schaltungen, physikalischen Modellen und Algorithmen aus der digitalen Signalverarbeitung können das Verständnis von Neurodynamiken erleichtern. / How recurrent neural networks can help to make autonomous robots move, will be investigated within this thesis. First, oscillators which are able to control four-legged robots will be dealt with, then homeostatic ring modules which control segmented robots, and finally monostable neural modules, which are able to drive complex motion sequences on robots with many degrees of freedom will be focused upon. The mathematical theory of neural modules will be addressed as well as their practical implementation on real robot platforms. This includes their embedding into a major framework and concrete aspects, like computational accuracy, timing and dependance on materials. Details on electronics will be given, so that individual robot systems can be built and equipped with an appropriate motion controller. It is another concern of this thesis, to shed a new light on the theory of recurrent neural networks, from the perspective of classical engineering science. Selective comparisons to analog electronic schematics, physical models, and digital signal processing algorithms can ease the understanding of neural dynamics.

A comprehensive and scalable solution for high-performance switched capacitor amplification is presented. Central to this discussion is the concept of ring amplification. A ring amplifier is a small modular amplifier derived from a ring oscillator that naturally embodies all the essential elements of scalability. It can amplify with accurate rail-to-rail output swing, drive large capacitive loads with extreme efficiency using slew-based charging, naturally scale in performance according to process trends, and is simple enough to be quickly constructed from only a handful of inverters, capacitors, and switches. In addition, the gain-enhancement technique of Split-CLS is introduced, and used to extend the efficacy of ring amplifiers in specific and other amplifiers in general. Four different pipelined ADC designs are presented which explore the practical implementation options and design considerations relevant to ring amplification and Split-CLS, and are used to establish ring amplification as a new paradigm for scalable amplification. / Graduation date: 2012 / Access restricted to the OSU Community, at author's request, from July 19, 2012 - July 19, 2013

A digital system is often required to operate under a specific frequency. A ring oscillator can be helpful in this circumstance because it can generate a signal with a specific frequency. However, a ring oscillator is also sensitive to the environment temperature. With the increasing requirement of accuracy and stability, many approaches appear worldwide to make a temperature-insensitive ring oscillator. This thesis project presents an approach to compensate the temperature effect on a Current Starved Ring Oscillator(CSRO). More concretely, we researched how to achieve temperature compensation for CSRO in a digitally-controlled configuration. A Phase Frequency Detector (PFD) block is adapted to sense the frequency difference between the reference frequency and CSRO frequency. Two Charge Pumps (CP)are used to quantify the difference in voltage signal. A Dynamic Comparator block compares the signals from CPs. A following Bidirectional Counter block can count up or down to change the current in CSRO by a four-bit signal. In the end, the CSRO can generate an oscillating signal at the appropriate frequency after some adaptation time. This proposed circuit was realized with AMS 0.35 um CMOS technology and simulated using the Cadence tools. Power consumption, temperature compensation analysis and voltage supply compensation analysis under different temperatures are also performed in the project.

Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014