The aim of the thesis is the design and realization of the oscilloscope module with wireless data transfer. One part of the thesis is a short overview of the different types of AD converters. The main part is focused on the hardware configuration that allows modification of the wireless module of the oscilloscope, and the possibility of using in the industrial zone. The design takes into account reducing of consumption and EMC compatibility.

This thesis investigates the use of field-programmable gate arrays (FPGAs) to implement a time-to-digital converter (TDC) with on-chip calibration and temperature correction.Using carry-chains on the Xilinx Kintex UltraScale architecture to create a tapped delay line (TDL) has previously been proven to give good time resolution.This project improves the resolution further by using a bit-counter to handle bubbles in the TDL without removing any taps.The bit counter also adds the possibility of using a wave-union approach previously dismissed as unusable on this architecture.The final implementation achieves an RMS resolution of 1.8 ps.

With the rapid development of mobile communication, sensors, and biomedical in recent years, the demand for accurate data information, highquality audio and image has become much more significant, which requires a high-precision Analog to Digital Converter (ADC) to process weak analog signals. As one of the core modules of ADC, the comparator’s precision, speed, stability, and noise play a key role in the performance of the whole circuit. Over the years, those performance has been improved a lot by both designing new architectures and using advanced fabrication technology. However, the conventional comparators occupy 50%-60% of the total energy consumption of EPC, even with advanced technology and lower supply voltage. In this thesis, a new type of energy-efficient comparator, called Edge-Pursuit Comparator (EPC), is proposed, which satisfies the need for low comparison energy. The design of EPC is based on a ring oscillator, when the EPC enters the evaluation mode, two signal edges with different propagation delays will chase in it until one overlaps the other, and finally generate a stable voltage level in each output node. The circuit is built and simulated in Cadence Virtuoso using cmos22fdsoi technology. The simulation results reveal that the energy consumed per comparison is dependent on the input differential voltage, and it can be as low as 7 fJ when vin = 50 mV, which is around ten times smaller compared with conventional comparators. In addition, as the power consumption is considerable when the two input voltages are very close, a promising improvement is applied to EPC, namely connecting every node with a variable capacitor, which is called Edge-Pursuit Comparator enhanced with Capacitor (EPCC). Cadence simulation results prove that EPCC can largely lower the energy consumption under a small vin while keeping input-referred noise the same. Therefore, a combination of EPC and EPCC is expected to have prospective applications in the energy-efficient area. / Med den snabba utvecklingen av mobil kommunikation, sensorer och biomedicin under de senaste åren har efterfrågan på korrekt datainformation, högkvalitativt ljud och bild blivit mycket mer betydande, vilket kräver en högprecision Analog till Digital Converter (ADC) för att bearbeta svaga analoga signaler. Som en av ADC:s kärnmoduler spelar komparatorns precision, hastighet, stabilitet och brus en nyckelroll i prestanda för hela kretsen. Under årens lopp har dessa prestanda förbättrats mycket genom att både designa nya arkitekturer och använda avancerad tillverkningsteknik. De konventionella komparatorerna upptar dock 50%-60% av den totala energiförbrukningen för EPC, även med avancerad teknik och lägre matningsspänning. I detta examensarbete föreslås en ny typ av energieffektiv komparator, kallad Edge-Pursuit Comparator (EPC), som tillgodoser behovet av låg jämförelseenergi. Designen av EPC är baserad på en ringoscillator, när EPC:n går in i utvärderingsläget kommer två signalkanter med olika utbredningsfördröjningar att jaga i den tills den ena överlappar den andra, och slutligen generera en stabil spänningsnivå i varje utgångsnod. Kretsen är byggd och simulerad i Cadence Virtuoso med hjälp av cmos22fdsoiteknik. Simuleringsresultaten visar att energiförbrukningen per jämförelse är beroende av ingångsdifferensspänningen och den kan vara så låg som 7 fJ när vin = 50 mV, vilket är cirka tio gånger mindre jämfört med konventionella komparatorer. Dessutom, eftersom strömförbrukningen är avsevärd när de två inspänningarna är mycket nära, tillämpas en lovande förbättring på EPC, nämligen att ansluta varje nod med en variabel kondensator, som kallas Edge-Pursuit Comparator förbättrad med kondensator (EPCC). Kadenssimuleringsresultat bevisar att EPCC till stor del kan sänka energiförbrukningen under en liten vin samtidigt som ingångsreferat buller hålls detsamma. Därför förväntas en kombination av EPC och EPCC ha potentiella tillämpningar inom det energieffektiva området.

Behovet för kraftplattor idag växer inom idrotts- och sportsammanhang såväl som inom medicinska sektorn. Problemet med majoriteten av kraftplattorna på marknaden idag är att de är dyra, samt stora och tunga. På Kungliga tekniska högskolans skola för medicinteknik och hälsosystem utvecklades en kraftplatteprototyp med Wii Balance Board i hopp om att vara billigare och kunna användas i medicinskt, terapeutiskt och idrottssyfte. Enligt konstruktören och uppdragsgivaren finns det ett behov att göra om denna prototyp genom att undersöka möjligheten till att använda komponenter som är billiga, tillgängliga för allmänheten men samtidigt är noggrann och pålitlig i mätningarna. I detta arbete undersöks möjligheterna samt konstrueras två prototyper för jämförelse och analys för att säkerställa pålitlighet och noggrannhet.  Två kraftplatteprototyper utvecklades, ena prototypen använde en HX711 som AD- omvandlare mellan lastcellerna på Wii Balance Boarden och ESP32 mikrokontrollern och den andra en AD7124-8 som AD-omvandlare mellan lastcellerna och ESP32 mikrokontrollern. Lastcellerna kopplades till dessa AD-omvandlare som sedan kopplades till en ESP32 mikrokontroller som tog emot datat och presenterade det i Arduino IDE samt i applikationen Blynk. Resultatet av arbetet visade att båda prototyperna är pålitliga och noggranna i viktmätningarna vid låga samplingsfrekvenser, men att AD7124-8 är betydligt mycket mer lämplig i idrott och medicinska syften på grund av dess höga samplingsfrekvens samt filtreringsalternativ för brus då det i dessa sammanhang är viktigt att kunna mäta snabba kraftförändringar. / The need for force plates is increasing today in the sports and medicine industry. The challenges with force plates are the price point and the immobility of them, they are often big and heavy. A force plate prototype with a Wii Balance Board was developed at Royal Institute of Technology’s school for biomedical engineering and health systems with the hope of achieving a cheaper solution that could be used in medical research and the sports industry. According to the constructor of the force plate prototype, there is a need to redo this prototype by doing research of using cheaper and more readily available components but at the same time be precise and trustworthy in measurements. The possibilities are evaluated in this work and two prototypes are constructed.  Two force plate prototypes were constructed, one of them used a HX711 AD-converter between the load cells of the Wii Balance Board and the ESP32 microcontroller and the other prototype used a AD7124-8. The load cells connected to the AD-converters and then to the ESP32 which showed the output values in the serial monitor of Arduino IDE and in the Blynk app. The results of the tests conducted showed that both prototypes provided a reliable and precise measurement of weight at low sample rates. But that the AD7124-8 was considerably more suitable for medicine research and sports research due to its capability to sample at high frequencies and noise filtering options, which is crucial when wanting to detect rapid changes in force.

Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works.

The diplomma thesis is dealing with possibilities of Signal to noise ratio measurement by method, which is based on direct measurement. It is chosen the most suitable method – signal and noise separation to two different parallel signal branches, where is measured signal strength in one branch and root mean square value in the other. The thesis is consisted of a concept of detail block scheme of Signal to noise ratio meter, which was designed in terms of theoretical knowledge. Particular functional blocks were circuit-designed, the active and passive parts were chosen and their function were described. There were made simulation and displayed input and output time flows. There is designed the whole connection of engineered Signal to noise ratio meter in the last part of my thesis. The double-sided board of printed circuit is contained too. It was created simple programme for supervisor micro-processor. Thereby were constructed complete bases for realization.

Nowadays, small autonomous underwater robots are strongly preferred for remote exploration of unknown and unstructured environments. Such robots allow the exploration and monitoring of underwater environments where a long term underwater presence is required to cover a large area. Furthermore, reducing the robot size, embedding electrical board inside and reducing cost are some of the challenges designers of autonomous underwater robots are facing. As a key device for reliable operation-decision process of autonomous underwater robots, a relatively fast and cost effective controller based on Fuzzy logic and proportional-integral-derivative method is proposed in this thesis. It efficiently models nonlinear system behaviors largely present in robot operation and for which mathematical models are difficult to obtain. To evaluate its response, the fault finding test approach was applied and the response of each task of the robot depicted under different operating conditions. The robot performance while combining all control programs and including sensors was also investigated while the number of program codes and inputs were increased.

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